> Markdown version of [/jobs/ext/4585405-software-engineer-ii](https://www.wearedevelopers.com/jobs/ext/4585405-software-engineer-ii). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Software Engineer II - **Company:** Cadence Design Systems, Inc. - **Location:** San Jose, CA, United States - **Salary:** $105,000.0 - $195,000.0 - **Contract:** Internship / Graduate position - **Skills:** Computer-Aided Design, Algorithm Design, Very-Large-Scale Integration, C++ (Programming Language), Computer Programming, Computer Engineering, Data Structures, Software Debugging, Linux, Electronic Design Automation, Perl (Programming Language), Python (Programming Language), Computational Geometry, Software Engineering, Software Systems, Tcl (Programming Language), Scripting, Information Technology, Physical Design - **Published:** November 5, 2026 - **Apply:** https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Software-Engineer-II_R57067-1 ## About the Role * MS in Computer Science, Electrical Engineering, Computer Engineering, or a related field * Strong programming skills in C/C++ * Strong foundation in algorithms, data structures, and problem-solving * Good understanding of software development and debugging in Linux/UNIX environments * Strong analytical and debugging skills * Ability to work effectively in a collaborative, team-oriented environment, * Coursework, research, internship, or project experience in VLSI CAD, physical design, algorithms, computational geometry, or optimization * Basic knowledge of digital IC design or physical design concepts * Experience with algorithm development or large-scale software development * Familiarity with scripting languages such as Tcl, Python, or Perl * Exposure to EDA tools or place-and-route flows is a plus, but not required ## Description Cadence Design Systems is looking for a highly motivated Software Engineer II to join the Innovus R&D team. Innovus is Cadence's flagship digital implementation platform, enabling customers to design advanced semiconductor chips from RTL to GDSII. In this role, you will contribute to the development of advanced power routing technologies for digital physical design, with an emphasis on power/ground routing, power network planning and creation, and power delivery optimization. You will work closely with experienced R&D engineers to develop algorithms and software solutions for challenging routing problems in advanced semiconductor designs. Key Responsibilities * Design and implement algorithms for advanced power routing and power optimization * Develop high-performance and scalable software using C/C++ on Linux/UNIX platforms * Debug, troubleshoot, and enhance existing features within the Innovus platform * Analyze performance bottleneck and improve quality of results, runtime, and robustness * Collaborate with cross-functional teams to define requirements, validate solutions, and deliver production-quality features