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# Senior DFT Design Engineer

- **Company:** Intel Corporation
- **Location:** Hillsboro, OR, United States
- **Experience:** Expert
- **Salary:** $141,910.0 - $172,860.0
- **Contract:** Internship / Graduate position
- **Skills:** Computer Programming, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Static Timing Analysis, Scripting
- **Published:** November 5, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3496678272&tx=UT5652THT&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences., Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 4+ years of industry experience OR Masters in Electrical Engineering, Computer Engineering or related STEM degree and 3+ years of industry experience OR PhD in Electrical Engineering, Computer Engineering or related STEM degree and 1+ years of industry experience.

Your experience should be in following

 * Scan, ATPG or other DFT features.
 * SoC or IP DFT design, integration or verification.
 * EDA tools such as Siemens Tessent or other ATPG tools, Synopsis VCS and/or other simulation or debug tools.

Preferred Qualifications:

Silicon enabling debug or test pattern development experience.

Design automation skills and proficiency in programming or scripting languages.

Structural design flows, including timing, routing, placement or clocking analysis.

High volume manufacturing requirements and test flows.

3D, media and display graphics pipelines.

SoC architecture.

## Description

We are looking for Senior DFT Design Engineers to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the GHI DFT group, you will be responsible for the following activities:

You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG

You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of ATPG content

Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs.

Participates in the definition of architecture and microarchitecture features of the block being designed.

Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Supports SoC customers to ensure high-quality integration of the GPU block., This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.