> Markdown version of [/jobs/ext/4588068-systems-solutions-architect](https://www.wearedevelopers.com/jobs/ext/4588068-systems-solutions-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Systems Solutions Architect - **Company:** Cadence Design Systems, Inc. - **Location:** San Jose, CA, United States - **Salary:** $185,500 - $344,500 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Systems Engineering, Audio Signal Processing, Microprocessors, Middleware, Firmware, Hardware Design, Systems Architecture, SystemC, Systems Integration - **Published:** November 5, 2026 - **Apply:** https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Systems-Solutions-Architect_R57101-1 ## About the Role * 12+ years in a leading architectural or system engineering role, with a demonstrable history of architecting complex systems from concept through to production. * Proven track record of designing integrated solutions where hardware features are explicitly built to support software mechanics, and vice versa. * Experience collaborating with, or leading performance modeling teams using SystemC, TLM, or custom cycle-accurate simulator infrastructures. * Experience in Physical AI (robotics, autonomous systems) delivering real-time Imaging and/or Radar (spatial awareness, tracking) and Advanced Audio processing. * Strong written and verbal communication skills. * Ability to travel up to 10% of the time, including internationally. ## Description * Define and own the system architecture for new hardware subsystems (compute, memory, interconnects, interfaces) and corresponding software stack (drivers, HAL, compiler runtimes, and middleware). * Architect solutions using the entire portfolio Cadence SSG IP, including compute (Tensilica DSPs and CPUs), Accelerators (Neo NPU and application-specific), interface IP, and memory controllers. * Partner closely with dedicated Performance Modeling teams to build cycle-accurate or transaction-level (TLM) simulations of the SoC subsystem. Use performance simulation data to identify bottlenecks before committing to silicon. * Hand off clear architectural specifications to experienced RTL/Hardware Implementation teams and Software/Firmware Engineering teams and serve as the bridge between these teams to ensure alignment. * Act as the final authority during system integration, validating that the implemented software stack extracts maximum performance from the physical hardware features. * Build scalable proof-of-concept (PoC) and reference designs that demonstrate the capabilities of the integrated Cadence IP platform. * Act as the technical liaison with Cadence engineering partners to influence future IP roadmaps based on emerging Physical AI trends (e.g., robotics, autonomous systems, edge transformers).