> Markdown version of [/jobs/ext/4589813-performance-architect-cpu-cluster](https://www.wearedevelopers.com/jobs/ext/4589813-performance-architect-cpu-cluster). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Performance Architect, CPU Cluster - **Company:** Tenstorrent Usa, Inc. - **Location:** Santa Clara, CA, United States (Remote available) - **Salary:** $100,000 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Application Performance Management, Multiprocessing, Reduced Instruction Set Computing, Systems Architecture, Network Switches, Caching - **Published:** November 5, 2026 - **Apply:** https://www.careerbuilder.com/job-details/performance-architect-cpu-cluster-santa-clara-ca--458a74b1-7a93-4a06-b762-adb76d9a322a ## About the Role CPU (Central Processing Unit), Semiconductors, RISC Processors, Artificial Intelligence (AI), CPU (Central Processing Unit), Problem Solving Skills, Leading Edge Technology, System Architecture, Architectural Services, RTL Design, * You have a strong foundation in CPU microarchitecture and performance, with an understanding of how cores, caches, interconnects, and memory systems interact. * You enjoy using modeling, simulation, and workload analysis to understand cluster-level performance bottlenecks and scaling challenges. * You're comfortable moving between detailed microarchitecture and broader system-level questions around latency, bandwidth, quality of service, utilization, and scalability. * You're analytical and hands-on, with the ability to turn large amounts of performance data into clear architectural recommendations. * You're a strong communicator who enjoys working across architecture, RTL, compiler, software, and system teams. ## Description * Analyze and optimize CPU cluster performance, including cache hierarchies, interconnects, coherence, and memory access behavior. * Build and use performance models and simulation environments such as Gem5 or equivalent to evaluate architectural concepts and identify performance opportunities. * Study real workloads to understand bottlenecks related to cache misses, coherence traffic, memory bandwidth, latency, contention, and core-to-core communication. * Lead architectural tradeoff studies across performance, scalability, bandwidth, latency, power, and implementation complexity. * Collaborate with CPU, cache, interconnect, memory, software, and system architects to translate performance analysis into concrete design decisions. What You Will Learn * How to architect, model, and optimize a multi-core CPU cluster from early performance exploration through implementation and silicon. * How cache coherence, interconnects, memory hierarchy, and core architecture interact to determine overall system performance. * How to model and reason about scaling across cores, including contention, bandwidth limits, latency, and workload behavior. * How architectural decisions at the cluster level translate into real-world application performance. * How Tenstorrent approaches scalable CPU and chiplet-based system architecture across compute, interconnect, and memory.