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# Silicon Photonics Engineer

- **Company:** Neurophos Inc.
- **Location:** Austin, TX, United States
- **Experience:** Experienced
- **Contract:** Permanent contract
- **Skills:** Comsol Multiphysics, Cadence Virtuoso, Signal Integrity, Network Switches, PIC Microcontroller, Hfss, Hardware Acceleration, Ansys, Model Inference
- **Published:** November 6, 2026
- **Apply:** https://startup.jobs/staff-silicon-photonics-engineer-receiver-rx-neurophos-10684025

## About the Role

* PhD in a relevant field, such as Electrical Engineering, Applied Physics, or Physics.
 * 3 years of relevant experience in high-speed silicon photonics, focused on photodetectors and receiver PICs.
 * Hands-on design experience with Ge-on-Si (or equivalent) high-speed photodetectors, including the trade-offs among responsivity, bandwidth, capacitance, and dark current.
 * Proficiency with photonic and device simulation tools (e.g., Lumerical/Ansys, COMSOL, Synopsys TCAD, or equivalent) and with circuit-level modeling of photodetectors.
 * Experience laying out and taping out in a silicon photonics foundry PDK (e.g., KLayout, gdsfactory, Cadence Virtuoso, or equivalent).
 * Working knowledge of optical receiver fundamentals: TIA interfacing, noise, sensitivity, and PAM4 signal integrity.

Preferred Skills

 * 5+ years of experience developing high-speed silicon photonics receivers or photodetectors.
 * Experience taking devices through the full design-to-tapeout-to-fabrication-to-test cycle.
 * Experience designing large or dense photodetector arrays, or free-space and surface-normal optical coupling to photonic chips.
 * Experience co-designing PDs with CMOS/SiGe TIAs in monolithic, flip-chip, or 3D-integrated receivers.
 * Experience with advanced detector platforms (e.g., avalanche photodiodes, III-V/Si heterogeneous detectors) or a track record of publications or patents in photodetectors and receivers.

## Description

Neurophos is looking for a Silicon Photonics Engineer to lead the receiver (Rx) photonic integrated circuit for our OPU platform, including the T100 optical AI inference chip. You will own the Rx PIC from photodetector device design through chip-level architecture: how light reaches the chip, how it is coupled and routed, and how large photodetector arrays convert it into clean, high-speed electrical signals for the TIAs. You will take designs through tapeout and silicon validation. Working closely with the electronic IC, optics, and packaging teams, you will balance bandwidth, sensitivity, noise, density, and power at the system level., * Define the Rx PIC architecture, including optical input coupling (free-space and waveguide), routing, demultiplexing where needed, and the layout of dense photodetector arrays, all against system-level link and power budgets.

 * Design and optimize high-speed photodetectors (e.g., Ge-on-Si PIN and avalanche, waveguide-coupled and surface-normal) for responsivity, dark current, capacitance, bandwidth, linearity, and saturation.
 * Model the device and receiver with optical, electrical, and RF simulation (e.g., Lumerical FDTD/CHARGE/INTERCONNECT, HFSS, TCAD), including photodetector equivalent circuits for co-design with the TIA.
 * Work with the electronic IC team on the PD-TIA interface (pad and interconnect parasitics, bias, input-referred noise, sensitivity), including flip-chip, 3D, and co-packaged integration.
 * Analyze array-level effects such as optical and electrical crosstalk, uniformity, thermal behavior, and yield, and define test structures and design-for-test features to measure them.
 * Lead layout, verification, and tapeout of Rx PIC test vehicles and product blocks in foundry silicon photonics PDKs.
 * Support die- and wafer-level characterization with the test team (responsivity, dark current, O/E bandwidth, sensitivity, BER), and use the measurements to calibrate models and improve the next design.
 * Evaluate new detector materials, structures, and coupling approaches that could improve receiver performance or density beyond what the current platform supports.