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# Senior CPU Design Engineer

- **Company:** NVIDIA Ltd.
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $168,000.0 - $264,500.0
- **Contract:** Permanent contract
- **Skills:** Very-Large-Scale Integration, Computer Engineering, Microarchitecture, Logic Synthesis of Circuits, Microprocessors, Digital Technology, Perl (Programming Language), Python (Programming Language), CPU Design, SystemVerilog, Verilog, Scripting, Physical Design
- **Published:** November 6, 2026
- **Apply:** https://www.juju.com/job/7_9A6D8B95D4A9EBF83ABE707194347F25

## About the Role

What we need to see: BS or MS in electrical engineering or computer engineering (or equivalent experience).
8+ years of proven experience in micro-architecture and RTL development of complex, high speed designs, ideally in CPU subsystems.
Exposure to Computer Architecture and Digital Systems design.
Highly proficient in logic design, Verilog and/or SystemVerilog, with a deep understanding of physical design and VLSI. Strengths in scripting languages such as Perl, Python.
Good communication and interpersonal skills.

## Description

The NVIDIA CPU team is looking for inquisitive, motivated engineers with design experience to build ground-breaking CPUs.
As a senior member of our design team, you will be responsible for the micro-architecture, design and implementation of high-performance, low power CPUs.
You will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks.
What you will be doing: Drive the micro-architecture definition, feasibility studies and documentation of CPU sub-systems.
Implement in RTL and coordinate execution with the verification team to ensure that the design is functional.
Exercise logic design skills to optimize and meet performance, timing and power targets.
Deliver a synthesis/timing clean design while working with the physical design team ensuring a routable and physically implementable design.
Support hardware engineering activities including chip floor plan, power/clock distribution, chip assembly, timing closure, power and noise analysis, and back-end verification.
Develop flows and tools as necessary in support of design activities.