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# Sr Staff Engineer, Program/Project Management- Test Readiness Lead

- **Company:** Celestica, Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Testing (Software), Computer Engineering, Software Debugging, Pareto Chart, Information Technology, Hardware Infrastructure
- **Published:** November 6, 2026
- **Apply:** https://www.austinjobsite.com/job.asp?id=3499540991&tx=KP2525FFP&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Technical Experience: 8+ years of dedicated engineering experience in Test Development, Functional Testing architecture, ATE hardware infrastructure, or NPI Test leadership inside high-density hardware industries., Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.

## Description

The single owner of test readiness for a programme, at rack or tray level. Issues the MTRS, sets coverage, and signs that the product can be tested at yield before any build is authorised., * Issue the MTRS with structural and functional coverage targets per insertion, before test development starts.

 * Agree the reduced-scope EVT test with design, software and the site, and report measured coverage and first pass yield at EVT exit.
 * Sign the Test Readiness Review before the Build Authorisation is issued.
 * Own test limits and guardband method with the design authority, and control the limit file against station-level edits.
 * Own golden unit designation and control, and the manufacturing diagnostics and provisioning package with Software.
 * Drive early-build debug to root cause within the agreed turnaround, and agree failure attribution at 8D closure.
 * Verify station correlation, Gage R&R and parametric data capture before the build.
 * Track NPI-phase DPPM, first pass yield and test time against budget for the programme.
 * Feed test escapes and coverage gaps back into the DFT rule set., * MTRS & Coverage: Translating design specifications into test requirements and defining structural/functional defect coverage across all assemblies.
 * Insertion Plans & TRR: Designing stage-by-stage test flows (ICT, FCT, Burn-in) and driving formal Test Readiness Reviews to secure milestone sign-offs.
 * Limit & Reference Control: Managing Golden/faulted units and applying statistical guard-banding, calibration, and Gage R&R for station stability.
 * NPI Yield & 8D: Monitoring First Pass Yield, building defect Pareto charts, and driving formal 8D root-cause corrective actions for line fallout.
 * Production Transfer: Packaging test software, fixture documentation, and SOPs to qualify and successfully hand off test lines to high-volume manufacturing.

Physical Demands

 * Duties of this position are performed in a normal office environment.
 * Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data.
 * Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.
 * Occasional travel may be required.