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# CPU Microarchitect, Vector And Matrix Compute

- **Company:** Tenstorrent Usa, Inc.
- **Location:** Santa Clara, CA, United States (Remote available)
- **Experience:** Expert
- **Salary:** $100,000
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Microarchitecture, Extract Transform Load (ETL), Microprocessors, Internet Protocol, Machine Learning, CPU Design, Performance Tuning, Software Architecture, Reduced Instruction Set Computing, Subsystems, Systems Architecture, High Performance Computing, Information Technology
- **Published:** November 6, 2026
- **Apply:** https://www.careerbuilder.com/job-details/cpu-microarchitect-vector-and-matrix-compute-santa-clara-ca--c1c39f8c-9bca-4f21-a4fe-00d6012e83f4

## About the Role

CPU (Central Processing Unit), Semiconductors, RISC Processors, Artificial Intelligence (AI), CPU (Central Processing Unit), Problem Solving Skills, Leading Edge Technology, Computer Systems, Performance Tuning/Optimization, IP (Internet Protocol), * Passionate about designing next-generation compute architectures for AI, HPC, and large-scale datacenter systems.

 * Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.
 * Comfortable making architectural decisions across CPU cluster and subsystems.
 * Collaborative technical leader who enjoys influencing cross-functional engineering teams.
 * Curious and driven to solve challenging performance, scalability, and system architecture problems.

What We Need

 * 5+ years of experience in CPU design for high-performance computing and AI acceleration.
 * Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads.
 * Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and interactions between CPUs and AI accelerators.
 * Experience defining architectural specifications and leading cross-functional teams from concept through silicon implementation.
 * Experience with RTL development with cutting edge AI frontier models.