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# Senior Solution Architect

- **Company:** HCL Technologies
- **Location:** Tampa, FL, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Code Coverage, Cyber Security, Data Centers, Software Debugging, Logic Synthesis of Circuits, Firmware, Internet Protocol, Systems Architecture, System on a Chip, Application Specific Integrated Circuits, Physical Design
- **Published:** November 6, 2026
- **Apply:** https://www.careerbuilder.com/job-details/senior-solution-architect-tampa-fl--6035fd06-fe0a-42c4-b3a8-3e83c1c78108

## About the Role

Budgeting, IP (Internet Protocol), System-on-a-Chip (SoC), Cost Allocation, System Architecture, Topology, Memory Hardware, Input/Output, Adjudication, Budget Management, * M.S./Ph.D. in EE/CE or equivalent experience; 20+ years in SoC/ASIC design with progressively senior architecture roles.

 * Demonstrated experience owning full-chip architecture for at least one shipped SoC (or major subsystem architecture on a large-scale SoC).
 * Strong grasp of digital design, low-power design techniques, memory/interconnect architecture, and physical design constraints (so tradeoffs are grounded in implementation reality, not just theory).
 * Proven ability to make and defend high-stakes tradeoff decisions under schedule/cost pressure, and to communicate them across technical and business audiences.

Preferred

 * Experience across multiple process nodes and multiple end markets (mobile, automotive, data center, edge AI).
 * Background that spans both hardware and software/firmware architecture (useful for HW/SW co-design tradeoffs).
 * Experience with formal system-level performance/power modeling tools (e.g., architectural simulators, power estimation frameworks).

## Description

The SoC Architect owns the system-level architecture of the chip: how its partitioned into subsystems/IP blocks, how area/power/timing/cost budgets are allocated across those partitions, and the tradeoff decisions that reconcile competing requirements from product, silicon, and software stakeholders., * Specification & Partitioning

 * Translate product/market requirements into a system architecture spec: block diagram, subsystem boundaries, interconnect topology (NoC/bus), memory hierarchy, and clock/power domain partitioning.
 * Decide what is custom silicon vs. licensed IP vs. reused block from prior designs, and define interface contracts (protocols, timing, power sequencing) between partitions.
 * Own the SoC-level floorplan intent (macro placement zones, I/O planning, hierarchy of physical blocks) in partnership with physical design leads.
 * Budgeting & Tradeoffs
 * Own top-down and bottom-up budget allocation for area, power (dynamic/leakage), timing (frequency targets per domain), and cost (die size, package, test time) across all blocks.
 * Run and adjudicate tradeoff studies (e.g., performance vs. power vs. area, cache size vs. latency, IP reuse vs. custom design) and make/own the final call when teams disagree.
 * Maintain the architecture "ledger" - a live tracking of budget vs. actual as blocks mature from RTL to layout to silicon, flagging overruns early and reallocating margin.
 * Cross-Domain Tradeoff Ownership
 * Balance competing needs from digital, analog/mixed-signal, DFT, verification, software/firmware, and packaging teams - SoC Architect is the tie-breaker when local optimization for one domain would hurt the system.
 * Own key architectural decisions: process node selection, IP sourcing strategy, memory/cache hierarchy, interconnect fabric choice, power domain/DVFS strategy, security architecture boundaries, and safety/reliability architecture (for automotive/industrial-grade parts).
 * Participate in DFM/DFT tradeoffs (test coverage vs. area/routing overhead) and yield-vs-performance tradeoffs with the Foundry Interface Lead and DFM teams.

Skill Requirements

 * Program-Level Technical Leadership
 * Chair/lead architecture review boards; drive sign-off milestones (architecture freeze, microarchitecture freeze, floorplan freeze).
 * Own the risk register for architectural decisions and drive contingency/mitigation plans (e.g., fallback IP options, spin plans).
 * Serve as the primary technical escalation point when subsystem teams cannot resolve interface or budget conflicts among themselves.
 * Interface with product management/marketing to communicate technical tradeoffs in business terms (cost, schedule, performance impact).
 * Documentation & Continuity
 * Own and maintain the architecture specification document set as the single source of truth through the program lifecycle.
 * Ensure architectural decisions and their rationale are documented for post-silicon debug, next-gen derivative planning, and knowledge transfer.