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# Performance & Debug Software Engineer - AI Inference

- **Company:** Positron Ai, Inc.
- **Location:** United States (Remote available)
- **Salary:** $200,000 - $300,000
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Profiling, Nvidia CUDA, Extract Transform Load (ETL), Software Debugging, Linux, Firmware, Field-Programmable Gate Array (FPGA), Python (Programming Language), Linux Kernel, Software Architecture, Regression Testing, Software Deployment, Application Specific Integrated Circuits, Distributed Inference, Perf (Linux), Machine Learning Operations, Model Inference
- **Published:** November 6, 2026
- **Apply:** https://www.builtincolorado.com/job/performance-debug-software-engineer-ai-inference/12101831?handler=ApplyRedirect

## About the Role

* Strong C++ and Python skills, with hands-on experience profiling and optimizing complex systems that exercise Linux VFIO interfaces..
 * Deep understanding of memory hierarchy, concurrency, data movement, batching, scheduling, and performance measurement.
 * Hands-on experience using profilers, counters, traces, and statistical methods to distinguish signal from noise.
 * Demonstrated ability to debug across application, runtime, driver, firmware, and hardware boundaries.
 * Experience bringing up software on new silicon, and debugging and analyzing performance optimizations in customer production deployments.
 * Enthusiasm for AI-accelerated software development, including using coding agents and orchestrating subagents to move faster without compromising engineering outcomes., * Experience with CUDA, HIP, Triton, GPU kernel development, distributed inference, or KV cache systems.
 * Familiarity with transformer inference, mixture-of-experts (MoE) models, model serving, FPGA or ASIC accelerators.
 * Working knowledge of Perfetto, Linux perf, eBPF, simulation, or hardware performance counters.

## Description

This engineer will improve end-to-end large language model (LLM) inference performance on Positron's custom AI accelerators, including our FPGA-based Atlas systems and our Titan systems built on the Asimov ASIC. The work spans hardware-accelerated attention, accelerator tuning, distributed KV cache, and scalable inference serving architectures. It covers profiling, algorithms, GPU-side data preparation, host-to-device data movement, runtime behavior, and measurement on production-relevant models.

You will join a small, performance-focused team that is expected to optimize the whole stack, and not merely tune isolated kernel interfaces. The goal is to sustain a repeatable path from observing workload symptoms to identifying root causes and creating measured improvements.

Key ResponsibilitiesPerformance Profiling and Optimization

 * Profile and optimize latency, throughput, utilization, and efficiency across hardware-accelerated attention, accelerator configuration, the device runtime, host software, and on-device execution.
 * Use performance counters, hardware and software traces, telemetry, and simulation to isolate regressions and validate fixes.

Distributed Inference and KV Cache

 * Develop and optimize distributed inference capabilities, including efficient KV cache management and data movement across heterogeneous hardware.

Benchmarking and Test Infrastructure

 * Build representative benchmarks and workload traces that expose bottlenecks in compute, memory, chip-to-chip interconnect, networking, scheduling, and model loading.
 * Partner with test engineers embedded in the team to turn performance findings into durable regression tests and release gates.