> Markdown version of [/jobs/ext/4609310-senior-software-engineer-hardware-tools-and-methodology-development](https://www.wearedevelopers.com/jobs/ext/4609310-senior-software-engineer-hardware-tools-and-methodology-development). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Senior Software Engineer, Hardware Tools and Methodology Development

- **Company:** NVIDIA Ltd.
- **Location:** United States
- **Experience:** Expert
- **Salary:** $136,000.0 - $218,500.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Computer Graphics, Perl (Programming Language), Python (Programming Language), Machine Learning, Process Driven Development, Software Engineering, Verilog, Scripting, Graphics Processing Unit (GPU), Application Specific Integrated Circuits, Parallel Computation, Software Coding
- **Published:** November 6, 2026
- **Apply:** https://www.careerbuilder.com/job-details/senior-software-engineer-hardware-tools-and-methodology-development-ca--c2550a99-5ca4-4913-851e-a460ac502096

## About the Role

Software Engineering, Develop Methodologies, Computer Graphics, Gaming, GPU (Graphics Processing Unit), Parallel Computing, Power Amplifier, Human Intelligence (HUMINT), Machine Learning, RTL Design, The NVIDIA Clocks group is looking for a dedicated and motivated Software developer with particular interest in algorithms and RTL Design. Understanding both Software and Hardware principles will be a key requirement for this role., * BS or MS (preferred) degree or equivalent experience in CE or EE

 * At least 3+ years of work experience
 * Strong coding skills in C++
 * Good understanding of ASIC Design and understanding of Verilog RTL
 * Strong interpersonal and collaboration skills.

Ways to stand out from the crowd:

 * Prior experience in RTL design (Verilog), verification and synthesis.
 * Proficiency in C++, Perl, Python, Make scripting.
 * Knowledge of Clocks/Resets design and verification

## Description

* Architect automated workflows for supporting deliverables to multiple cross functional teams
 * Improve algorithms (in C++) for automated connectivity, auto logic insertion and post processing Verilog RTL
 * Improve quality of existing tools and flows used by the team