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# Software Engineer - RISC-V Random Test Generator

- **Company:** Qualcomm
- **Location:** Cupertino, CA, United States (Remote available)
- **Experience:** Experienced
- **Contract:** Permanent contract
- **Skills:** Systems Engineering, Encodings, Computer Engineering, Hypervisor, Python (Programming Language), CPU Design, Object-Oriented Software Development, Reduced Instruction Set Computing, Software Engineering, Virtual Memory, Information Technology
- **Published:** November 7, 2026
- **Apply:** https://www.juju.com/job/28_25197_63e91424d4bc10c2b159b0201d6e5385

## About the Role

* 2-5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
 * Solid Python 3 skills; comfort with generator-based coroutines and object- oriented design patterns.
 * Working knowledge of the RISC-V ISA: instruction encoding formats (R/I/S/B/ U/J, compressed, vector), CSR semantics, privilege levels (M/S/U), and the memory model. Alternatively, similar knowledge for x86 or ARM.
 * Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.
 * Exposure to random test generation flows or ISS/RTL co-simulation is a plus., * Compiler development experience.
 * Understanding of hypervisor and/or AIA/IMSIC interrupt architecture.
 * Familiarity with constraint-propagation libraries., * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
 * Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
 * PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

## Description

About the Role You will contribute to a Python-based random test generation (RTG) framework and its companion assembler library that together form the core of a RISC-V CPU design-verification toolchain. The RTG drives a JIT-style, simulator- coupled generator that produces ELF binaries exercising the RVA23.1 ISA - including privileged modes, virtual memory, interrupts, vector, and cryptography extensions. The assembler library provides the bit-accurate instruction encoding layer that the RTG and other tools consume., * Implement new generation objects for RISC-V extensions; common micro-architectural scenarios; and complex data/control-flow composable idioms.

 * Add instruction forms and encodings to the python companion assembler and verifying bit-level correctness against the RISC-V ISA spec.
 * Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
 * Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
 * Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic (register allocators, address-space managers, data fillers)., To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.