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# Senior RTL Design Engineer

- **Company:** IC Resources
- **Location:** San Francisco, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Software Debugging, Dynamic Random-Access Memory, Formal Verification, SystemVerilog
- **Published:** November 7, 2026
- **Apply:** https://www.juju.com/job/28_25303_464ccc0799cf9c2496d367079d1a8dfd

## About the Role

* BS/MS in EE/CE, 8+ years of RTL design in advanced SoCs.
 * Strong SystemVerilog coding and micro-architecture skills.
 * Proven experience with HBM (2/3), LPDDR (5/6), DDR (4/5).
 * Solid grasp of timing closure, CDC, power optimization.
 * Familiar with synthesis, lint, and UVM/verification methodologies.

## Description

* Architect and implement memory controllers for HBM2E/3, LPDDR5/6, and DDR5.
 * Deliver RTL from spec to tape-out: coding, simulation, synthesis, optimization.
 * Integrate memory PHY, interposer, and DRAM interfaces into SoC.
 * Collaborate with architecture, verification, and PD teams to close timing and power.
 * Debug across pre- and post-silicon phases; ensure first-pass success.
 * Contribute to other subsystems as gaps arise.