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# Senior Principal Software Engineer

- **Company:** Cadence Design Systems, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Unit Testing, C++ (Programming Language), Computer Programming, Concurrent Computing, Distributed Computing Environment, Simulation Software, Software Engineering, Static Timing Analysis, SystemVerilog, Verilog, Multithreading, Information Technology
- **Published:** November 7, 2026
- **Apply:** https://www.juju.com/job/28_25197_f6043ec3b403da48a3b3e02c83df3d9a

## About the Role

MS/PhD in Computer Science or Electrical Engineering. MS in Computer Science or Electrical Engineering with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience 5+ years of experience in EDA software development. Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool. Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog. Experience in multi-threaded/ concurrent programming. Ability to quickly learn new technologies and adapt to project requirements. Prior experience with RTL/logic simulation software development is an added plus.

## Description

Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features. Enhance and support Timing Constraints Verification technology used inside Xcelium simulator. The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi-billion-node graphs. Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint. Collaborate with global team members to deliver high-quality results in a distributed environment. Write Specifications and Unit Tests for your code.