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# Jr. FPGA Developer (Compute Test, North Reading)

- **Company:** Teradyne Inc.
- **Location:** North Reading, MA, United States
- **Experience:** Starter
- **Salary:** $98,700.0 - $157,900.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Software Debugging, Logic Synthesis of Circuits, Formal Verification, Field-Programmable Gate Array (FPGA), PCI Express, Signal Integrity, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Software Version Control
- **Published:** November 7, 2026
- **Apply:** https://www.juju.com/job/1_teradyne3-1433744100

## About the Role

We seek individuals who share our passion and determination.
Our commitment to customer success drives us to go the extra mile.
If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

 + 2+ years of hands-on experience in FPGA design and development.
 + Working knowledge of Verilog/SystemVerilog for design and debugging.
 + Exposure to AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
 + Understanding of digital design fundamentals and the ability to interpret schematics.
 + Some exposure to high-speed interfaces such as PCIe, DDR, SerDes, or similar technologies and familiarity with protocols such as AXI4, USB, I2C, and SPI.
 + Basic experience bringing up or debugging FPGA designs on hardware platforms.
 + Basic TCL and Python scripting skills and experience with version control systems.
 + Strong communication and collaboration skills, with an interest in developing system-level thinking and the ability to debug across FPGA, board, and software boundaries.
 + Preferred: coursework or project experience with SystemVerilog-based verification methodologies such as UVM; familiarity with FPGA SoCs and embedded processor subsystems; exposure to ATE or measurement equipment design; a basic understanding of signal integrity and high-speed serial interfaces; or familiarity with AI tools for engineering design.