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# RTL Design Engineer

- **Company:** Acceler8
- **Location:** Palo Alto, CA, United States
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Software Debugging, Digital Electronics, Logic Synthesis of Circuits, Hardware Design, Static Timing Analysis, System on a Chip, SystemVerilog, Verilog, Graphics Processing Unit (GPU), Application Specific Integrated Circuits, Large Language Models, Concurrency, State Machines, Computer Equipment, Physical Design, Model Inference
- **Published:** November 7, 2026
- **Apply:** https://www.juju.com/job/28_25197_53c05da1ae61cef6d65439c5e0303b9f

## About the Role

* Extensive experience in digital hardware design, with significant hands-on ownership of ASIC or SoC RTL development.
 * Strong proficiency in Verilog and/or SystemVerilog.
 * Proven ability to develop complex RTL from architectural specifications through implementation.
 * Deep understanding of digital microarchitecture, including datapaths, state machines, control logic, concurrency, and cycle-level behavior.
 * Strong knowledge of power, performance, and area (PPA) optimization and how RTL design choices influence physical implementation.
 * Experience debugging complex RTL issues and resolving functional or timing-related challenges.
 * Demonstrated collaboration with verification, microarchitecture, and physical design teams.
 * Staff-to-Principal-level technical judgment, combined with a willingness to remain highly hands-on in RTL design and debugging., * Experience designing AI accelerators, inference ASICs, GPUs, or other high-performance compute silicon.
 * Familiarity with LLM inference workloads and specialized compute architectures.
 * Experience with synthesis, static timing analysis, and physical design feedback.
 * Previous involvement in successful ASIC/SoC tapeouts.
 * Background working on first-generation silicon or early-stage hardware development.
 * Experience collaborating across architecture, design verification, and physical implementation.

## Description

An early-stage, venture-backed AI semiconductor startup is seeking an experienced RTL Design Engineer to help develop a next-generation chip purpose-built for large language model (LLM) inference.

The company is developing a specialized AI accelerator alongside its supporting software stack, with a focus on delivering efficient, high-performance inference.

This is a hands-on engineering role offering significant ownership across digital design, microarchitecture, verification, and physical implementation. You'll play a key role in bringing the company's first generation of silicon from architectural concepts through implementation and tapeout., * Translate high-level architectural specifications into detailed block-level microarchitecture and synthesizable RTL.

 * Design, implement, and optimize complex datapaths, control logic, and inter-block interfaces.
 * Make architectural and implementation trade-offs involving throughput, latency, power, area, and timing.
 * Own RTL development, debugging, and integration for significant portions of the ASIC/SoC design.
 * Collaborate with verification engineers to define expected functionality, debug failures, and resolve complex corner cases.
 * Work closely with physical design teams to analyze synthesis results, timing constraints, and implementation feedback.
 * Drive design improvements based on timing, power, and area requirements.
 * Take ownership of assigned design blocks through integration, verification closure, and tapeout readiness.
 * Document key design decisions, implementation risks, and technical trade-offs., * Opportunity to help develop a purpose-built LLM inference accelerator from the ground up.
 * Significant ownership of RTL and microarchitecture for first-generation silicon.
 * Work directly with a highly technical founding engineering team.
 * Influence key architectural decisions, design methodologies, and implementation strategies.
 * Hands-on engineering environment with broad technical exposure and minimal organizational layers.
 * Opportunity to make a meaningful impact on the development of next-generation AI computing hardware.

Hiring Process

The interview process typically consists of two to three conversations, including technical discussions covering previous projects, RTL design experience, and engineering problem-solving.