> Markdown version of [/jobs/ext/4619880-senior-fpga-engineer](https://www.wearedevelopers.com/jobs/ext/4619880-senior-fpga-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior FPGA Engineer - **Company:** Cisco Systems, Inc. - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $154,900 - $225,300 - **Contract:** Permanent contract - **Skills:** Bash Shell, Computer Programming, Software Debugging, Linux, Field-Programmable Gate Array (FPGA), Python (Programming Language), SystemVerilog, Tcl (Programming Language), Toolchain, Verilog, Vivado, Scripting, Cisco - **Published:** November 7, 2026 - **Apply:** https://jobs.localjobnetwork.com/apply/add/88809149/1 ## About the Role * Bachelor's degree in electrical engineering with 7+ years of relevant experience or master's degree in electrical engineering with 4 + years of relevant experience * Experience in full-lifecycle FPGA design. * Experience writing structured, reusable, and optimized Verilog * Expertise with vendor toolchains, such as Vivado, Quartus or Libero * Experience with timing closure and writing timing constraints * Experience with lab work using tools such as oscilloscopes, logic analyzers, programming dongles and their SW apps Preferred Qualifications: * Comfortable working in a Linux environment * Experience with scripting languages - shell, python, Tcl etc. * Experience writing test benches or running simulations * Has worked with more than one FPGA vendor * Previous experience with schematic design or system design ## Description FPGA Engineers serve a range of roles at Cisco, from IP creators and architects, to solution integrators, going from concept to production, guiding in solution verification, and ensuring that our products meet Cisco and Industry quality standards. * Drive innovation includes but not limited to FPGA design, RTL development (Verilog/SystemVerilog), FPGA architecture, synthesis, timing closure, simulation, verification, and hardware lab debugging. * Work cross-functionally with system designers, diagnostics engineers, customer escalation engineers, and external vendors to ensure robust test methodology and timely issue mitigation, resulting in high product quality and enabling next generation solutions. * Work independently using best practices, with minimal guidance and direction