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# ASIC Emulation and Verification Engineer

- **Company:** Broadcom
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $121,900 - $195,000
- **Contract:** Permanent contract
- **Skills:** Bash Shell, Databases, Computer Engineering, Software Debugging, Perl (Programming Language), Emulators, Firmware, Formal Verification, Hardware Description Language, Joint Test Action (IEEE Standards), Python (Programming Language), Log Files, Subsystems, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Application Specific Integrated Circuits, Hardware Acceleration, Front End Software Development
- **Published:** November 7, 2026
- **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-CA-San-Jose-Innovation-Drive/ASIC-Emulation-and-Verification-Engineer_R027621

## About the Role

* Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 8 years of hardware description or verification experience.
 * OR Master's Degree in a related field with a minimum of 6 years of relevant experience.

Preferred Skillsets & Technical Knowledge

 * Emulation Platforms: Deep hands-on experience with the Cadence Palladium enterprise emulation platform (e.g., Palladium Z1/Z2 or newer systems).
 * Front-End Flows: Strong proficiency in hardware description languages (Verilog / SystemVerilog) and hardware synthesis concepts for emulation mapping.
 * Verification Methodologies: Proven experience with UVM (Universal Verification Methodology) simulation frameworks, assertion-based testing (SVA), and metric-driven coverage closure.
 * Scripting & Tool Automation: Expertise in Python, Perl, Bash, or Tcl to parse log files, automate compiler tools, and manage massive regression databases.
 * Hardware Architecture: Solid understanding of AMBA subsystem protocols (AXI, AHB, APB) and processor interfaces to safely configure memory and clock domains inside the emulator.

## Description

We are seeking an experienced ASIC Emulation and Verification Engineer to bridge the gap between simulation and hardware acceleration. Your primary responsibility will be bringing up complex ASIC IP and SoC designs on Cadence Palladium emulation platforms, converting the RTL database into emulation-ready models, and executing high-speed hardware acceleration. Additionally, you will support the core pre-silicon team by performing standard UVM-based simulation, verification closure, and debugging tasks., * Palladium Emulation & Bring-up: Compile, synthesize, and map complex RTL databases onto Cadence Palladium hardware acceleration systems. Resolve compilation errors, manage clocking/memory overrides, and successfully bring up full-chip and sub-system emulation models.

 * Firmware Co-Verification: Partner closely with firmware engineering teams to accelerate early FW bring-up on the Palladium platform. Provide hardware models, map memory spaces, and configure virtual debuggers (like JTAG) to allow teams to boot low-level bootloaders, drivers, and operating systems well before physical silicon is available.
 * Standard Simulation Verification: Perform traditional pre-silicon verification tasks using SystemVerilog and UVM. Author test cases, develop monitors/checkers, and debug RTL anomalies using waveform viewers.
 * Debug & Triage: Diagnose complex hardware, testbench, and environment issues on Palladium using advanced hardware-debugging features. Root-cause failures across both simulation and emulation environments.
 * Infrastructure & Automation: Build and maintain automated scripts to seamlessly compile the RTL database and launch Palladium regressions. Manage database hand-offs between design release teams and the emulation environment.
*