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# Founding RTL Design Engineer

- **Company:** 80Twenty LLC
- **Location:** San Francisco, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Software Debugging, Python (Programming Language), OpenAI, SystemVerilog, Tcl (Programming Language), Scripting
- **Published:** November 7, 2026
- **Apply:** https://www.juju.com/job/28_25303_7663a2b24ca75257b1613eecf6d88696

## About the Role

* Has 4-10+ years of RTL design or verification experience using System Verilog and industry-standard flows.
 * Has strong debugging, scripting (Python/TCL) and automation skills.
 * Will thrive in a fast-moving, high-impact startup environment with minimal process and high technical stakes.
 * Is excited by the idea of joining a founding engineering team-helping build the function, not just join it.
 * Is comfortable collaborating globally and working across silos (hardware, verification, software/agents).

## Description

* Define and build the RL environment, product catalog, including scope, difficulty, and learning objectives for agents for each semiconductor environment (e.g., AXI, DMA, specialized modules - e.g. matrix multiplier core in AI accelerators)
 * Define realistic tasks for agents to learn within each environment to automate hardware engineering
 * Manage a team to execute the design and verification of each module and SoC and their agent tasks
 * Collaborate with frontier AI researchers from labs like OpenAI and Anthropic to make sure the expected behavior is learned for useful hardware engineering automation
 * Excitement and urgency around a ground breaking start up!