> Markdown version of [/jobs/ext/4625721-principal-ai-network-architect](https://www.wearedevelopers.com/jobs/ext/4625721-principal-ai-network-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal AI Network Architect - **Company:** Microsoft - **Location:** Boise, ID, United States - **Experience:** Expert - **Salary:** $139,900.0 - $274,800.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Microsoft Online Services, Computer Engineering, Network Congestion, Firmware, InfiniBand, Network Planning and Design, Remote Direct Memory Access, Signal Integrity, Systems Architecture, Systems Integration, AI Infrastructure, IEEE 802.3, Backend - **Published:** November 7, 2026 - **Apply:** https://www.juju.com/job/28_25303_9a8a158122b2c75b495e148880de4a2e ## About the Role * Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR Master's Degree in the same fields AND 7+ years technical engineering experience OR equivalent experience. * 5+ years of experience in designing AI backend networks and integrating them into large-scale GPU systems., Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter., * Proven expertise in system architecture across compute, networking, and accelerator domains. * Deep understanding of RDMA protocols (RoCE, InfiniBand), congestion control (DCQCN), and Layer 2/3 routing. * Experience with optical interconnects (e.g., PSM, WDM), link budget analysis, and transceiver integration. * Familiarity with signal integrity modeling, link training, and physical layer optimization. * Experience architecting backend networks for AI training and inference workloads, including Hamiltonian cycle traffic and collective operations (e.g., all-reduce, all-gather). * Hands-on design of high-radix switches ( 400Gbps per port), orthogonal chassis, and cabled backplanes. * Knowledge of chip-to-chip and chip-to-module interfaces, including error correction and equalization techniques. * Experience with custom NIC IPs and transport layers for secure, reliable packet delivery. * Familiarity with AI model execution pipelines and their impact on pod-level network design and latency SLAs. * Prior contributions to hyperscale deployments or cloud-scale AI infrastructure programs. Hardware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. For the San Francisco Bay Area and New York City metropolitan area, the base pay range is USD $188,000 - $304,200 per year. ## Description * Technology Leadership - Spearhead architectural definition and innovation for next-generation GPU and AI accelerator platforms, with a focus on ultra-high bandwidth, low-latency backend networks. Drive system-level integration across compute, storage, and interconnect domains to support scalable AI training workloads. * Cross-Functional Collaboration - Partner with silicon, firmware, and datacenter engineering teams to co-design infrastructure that meets performance, reliability, and deployment goals. Influence platform decisions across rack, chassis, and pod-level implementations. * Technology Partnerships - Cultivate deep technical relationships with silicon vendors, optics suppliers, and switch fabric providers to co-develop differentiated solutions. Represent Microsoft in joint architecture forums and technical workshops. * Architectural Clarity - Evaluate and articulate tradeoffs across electrical, mechanical, thermal, and signal integrity domains. Frame decisions in terms of TCO, performance, scalability, and deployment risk. Lead design reviews and contribute to PRDs and system specifications. * Industry Influence - Shape the direction of hyperscale AI infrastructure by engaging with standards bodies (e.g., IEEE 802.3), influencing component roadmaps, and driving adoption of novel interconnect protocols and topologies.