> Markdown version of [/jobs/ext/4626553-r-d-engineer-hardware-4](https://www.wearedevelopers.com/jobs/ext/4626553-r-d-engineer-hardware-4). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# R&D Engineer Hardware 4

- **Company:** Broadcom
- **Location:** Chandler, AZ, United States
- **Experience:** Experienced
- **Salary:** $109,700 - $175,500
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Data Analysis, C++ (Programming Language), Computer Programming, Databases, Information Engineering, Electronic Design Automation, Experimental Data, Python (Programming Language), Machine Learning, Performance Tuning, Broadcom, Cadence Virtuoso, Static Timing Analysis, Test Data, Multivariate Regression, Deep Learning, Generative AI, Information Technology, Modeling and Simulation
- **Published:** November 7, 2026
- **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-AZ-Chandler-North-Juniper-Drive/R-D-Engineer-Hardware-4_R027591-1

## About the Role

* Spice modeling and simulation: Must have experience in spice modeling tools, Cadence Virtuoso and familiarity with Primetime STA tools., * Education: MS plus 6 years experience OR Ph.D. plus 3 years experience in Electrical Engineering, Computer Science or a related field Top-tier semiconductor research institution, e.g. Stanford, UC Berkeley, MIT, Purdue, UIUC preferred.
 * Yield & Telemetry Experience: Proven track record in the semiconductor industry specializing in silicon macro characterization and SoC telemetry analysis.
 * Advanced Analytics: Deep expertise in applying Machine Learning and Artificial Intelligence techniques (e.g., deep learning, anomaly detection, multivariate regression) to physical hardware datasets.
 * Data Engineering Skills: Strong programming skills in Python, R, or C++ and hands-on experience handling massive databases.
 * Domain Knowledge: Deep understanding of semiconductor manufacturing processes, wafer fabrication, DFM practices, and electronic design automation (EDA) tools.

## Description

Broadcom is seeking a highly specialized semiconductor professional with experience in predicting wafer-level yield and optimizing PPA, from SoC telemetry and volume ATE production test data. We require deep experience in analyzing silicon architecture, static timing analysis (STA), and silicon telemetry, using advanced data analysis tools, where the goal will be to develop predictive yield and performance optimization tool sets. You will design and deploy ML, DL, and GenAI tools that translate silicon data into actionable optimized strategies., * Predictive Yield Modeling: Design, build, and deploy ML, DL, and GenAI models to predict and maximize wafer-level yield using large-scale SoC telemetry data.

 * Telemetry Data: Organize, clean, and analyze large, multi-source sensor databases and provide input on future telemetry requirements.
 * Circuit Telemetry & Silicon Expertise: Interpret complex parametric data, on-chip sensor readouts, and circuit telemetry to isolate failure mechanisms and marginalities.
 * Cross-Functional Collaboration: Partner with foundry, product engineering, design-for-manufacturing (DFM), DFT engineering teams to drive yield and PPA strategies.
 * Innovate, Scale, Deploy: Develop, qualify and productize experimental data workflows, and work with teams to release to scalable production.