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# Datacenter Compute SoC Architect

- **Company:** Mediatek Inc
- **Location:** San Jose, CA, United States
- **Experience:** Experienced
- **Salary:** $211,000
- **Contract:** Permanent contract
- **Skills:** Architectural Patterns, C++ (Programming Language), Cloud Computing, Cloud Engineering, Computer Engineering, Data Centers, Computer Data Storage, Ethernet, Firmware, PCI Express, Software Architecture, Reduced Instruction Set Computing, Systems Architecture, SystemC, Virtualization Technology, Information Technology
- **Published:** November 7, 2026
- **Apply:** https://www.juju.com/job/28_25196_5c50860d46eb939f30a05a27e4b7ef80

## About the Role

* Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
 * Experience: 10+ years of proven industry experience in SoC, Compute/CPU, or system architecture, with a minimum of 3 years focusing on high-performance server, datacenter, or network processor SoCs.
 * Deep understanding of high-performance CPU architectures (ARM, x86, or RISC-V) or Compute architectures.
 * Extensive knowledge of coherent fabrics and interconnects (e.g., ARM AMBA CHI, AXI, proprietary NoCs).
 * Strong expertise in memory hierarchy, cache coherency protocols, and main memory technologies (DDR4/5, LPDDR, HBM).
 * Solid understanding of high-speed I/O interfaces (PCIe, CXL, Ethernet).
 * Communication: Exceptional written and verbal communication skills, with the ability to distill complex architectural concepts into clear specifications for cross-functional teams.

## Description

* SoC Architecture Definition: Lead the architectural definition of next-generation datacenter Compute SoCs, including core/instance counts, cache hierarchies, coherent interconnects, and memory subsystems.
 * IP Selection & Integration: Define requirements and drive decisions for third- party and internal IPs (e.g., PCIe Gen 5/6, CXL, DDR5/HBM controllers, Network-on-Chip/NoC, and security enclaves).
 * PPA Optimization: Conduct rigorous Power, Performance, and Area (PPA) trade-off analysis to ensure the SoC meets strict datacenter efficiency and performance-per-watt targets.
 * Advanced Packaging Strategy: Collaborate with packaging teams on multi-die/chiplet-based architectures, die-to-die (D2D) interconnect protocols (e.g., UCIe), and advanced thermal solutions.
 * HW/SW Co-Design: Partner closely with firmware, OS, and cloud infrastructure software teams to ensure the hardware architecture optimally supports modern hypervisors, cloud-native workloads, and virtualization technologies.
 * Performance Modeling: Work with the performance modeling team to define use cases, guide the creation of C++/SystemC architectural models, and analyze simulation data to identify bottlenecks.
 * Technical Leadership: Write detailed architecture specifications and serve as the technical lead during the RTL implementation, verification, and silicon bring-up phases.