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# Senior Hardware Engineer

- **Company:** Microsoft
- **Location:** Mountain View, CA, United States
- **Experience:** Expert
- **Salary:** $119,800 - $234,700
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Artificial Intelligence, Microsoft Azure, Microsoft Online Services, Cloud Computing, Computer Engineering, Data Centers, Software Debugging, Logic Synthesis of Circuits, Python (Programming Language), Microsoft Office, Cloud Services, Tcl (Programming Language), Information Technology, Front End Software Development, Physical Design
- **Published:** November 7, 2026
- **Apply:** https://www.jobmonkeyjobs.com/career/28169459/Senior-Hardware-Engineer-California-Mountain-View-1210

## About the Role

* Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:

 * Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
 * This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable., * Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
 * 5+ years of experience in silicon CAD, physical design (logic synthesis), or design verification flows using tools such as Synopsys Fusion Compiler/Design Compiler and/or Cadence Genus/Innovus
 * 3+ years of hands-on experience with formal equivalency checking tools (Synopsys Formality and/or Cadence Conformal) in advanced process nodes
 * Proficiency in scripting and automation using Tcl and Python for developing and debugging production CAD flows
 * Experience with ECO flows, including functional-metal ECO and low-power (UPF-aware) equivalency verification
 * Experience qualifying and deploying EDA tool releases and working with vendor application engineers to drive issue resolution; familiarity with both Synopsys and Cadence equivalency tools
 * Effective communication and collaboration skills, with the ability to work effectively with distributed design and CAD teams and translate complex tradeoffs into clear next steps
 * Experience supporting multiple concurrent tapeouts and familiarity with cloud-based EDA compute environments

#AHSI

## Description

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.

The Methodology, Infrastructure, Silicon Engineering, and Labs engineering (MILE) team delivers the physical design CAD flows, tools, and infrastructure that Microsoft's silicon design teams use to take advanced-node chips from RTL to tapeout. Within MILE, the Physical Design (PD) CAD signoff group owns logic signoff, including formal equivalency checking, ECO verification, and low-power verification. Our flows are how design teams prove their silicon is functionally correct before tapeout, so quality here directly protects schedule, cost, and silicon quality across Microsoft's cloud and AI programs.

We are looking for a Senior PD CAD Equivalency Engineer to own and evolve our formal equivalency flows, working with design teams and EDA vendors to deliver reliable, high-quality equivalency checking for Microsoft's next-generation silicon.

Responsibilities

 * Own the end-to-end formal equivalency CAD flow, including RTL-to-netlist, netlist-to-netlist, functional ECO, and low-power (UPF-aware) verification, for Microsoft's silicon programs
 * Develop, debug, and maintain production flows and automation in Tcl and Python for Synopsys Formality and Cadence Conformal, including handling of complex design classes
 * Partner with physical design, front-end/synthesis, and signoff teams and with EDA vendors (Synopsys, Cadence) to qualify new tool releases, resolve critical tool issues, and support design teams through tapeout closure
 * Independently drive technical decisions for the equivalency domain, identify root causes of ambiguous tool behavior, and define clear paths to resolution; mentor and serve as a backup for other engineers in the team
 * Deliver measurable improvements in flow quality, runtime, and reliability, including regression coverage, documentation, and support turnaround for design teams