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# System Engineering / Product Definer -- High-Power Management

- **Company:** Critical Path Consultants, Inc.
- **Location:** San Francisco, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Altium Designer, Application Notes, Systems Engineering, Software Debugging, Microprocessors, OrCAD, Performance Tuning, Signal Integrity, Software Requirements Analysis, Graphics Processing Unit (GPU), Ansys, Network Server
- **Published:** November 7, 2026
- **Apply:** https://www.thejobnetwork.com/job/d4e39a4f-a11f-424d-842f-f4569feb1c40/system-engineering-product-definer-highpower-management

## About the Role

You will bridge the gap between silicon design, advanced multi-die packaging, product/test engineering, and tier-1 computing clients. The ideal candidate possesses deep expertise in both Silicon (Si) and Gallium Nitride (GaN) power devices, advanced multi-chip packaging, and Smart Power Stage (SPS) topologies., * Education: B.S. in Electrical Engineering (M.S. or Ph.D. preferred with a focus on Power Electronics).

 * Experience: 10+ years of hands-on experience in high-power management IC development and application engineering.
 * Domain Expertise:
 * Proven track record in high-density power solutions for AI servers, GPUs, CPUs, and enterprise computing.
 * Deep technical mastery in both Si-based MOSFETs/IC topologies and GaN power devices.
 * Strong familiarity with multiphase buck converters, switched-capacitor architectures, and point-of-load (PoL) topologies.
 * Lab Skills: Expert-level capability in bench testing, high-bandwidth signal integrity measurements, loss breakdown analysis, thermal imaging, and high-frequency noise troubleshooting.
 * Packaging Knowledge: Deep understanding of power module assembly, parasitic inductance minimization, thermal dissipation paths, and layout constraints for LGA, QFN, FO-PLP, and chip-embedded packages.
 * Work Experience: Direct experience at leading power semiconductor organizations (e.g., Infineon, Renesas, Monolithic Power Systems (MPS), Alpha and Omega Semiconductor (AOS), Analog Devices, or similar)., * Direct experience working on power delivery architectures for low-voltage, ultra-high-current processor rails (e.g., sub-1V, 500A+ transient profiles).
 * Strong familiarity with board-level layout design (Altium, Cadence Allegro) and power delivery network (PDN) simulation tools (SIMPLIS, SPICE, Ansys Q3D).
 * Based in or willing to travel regularly to the San Francisco Bay Area.

## Description

* Bench Characterization & Diagnostics: Lead hands-on lab characterization, debugging, and performance optimization of Smart Power Stages, driver ICs, and multiphase controllers under real-world AI workload dynamics.
 * Next generation, innovative product definition to solve the challenges related to AI based systems
 * Silicon & GaN Evaluation: Evaluate and benchmark high-frequency, high-power density Si and GaN-based power stages, optimizing for power density, transient response, efficiency, and thermal dynamics.
 * Cross-Functional Collaboration: Partner closely with IC Design, Package Engineering, Systems Engineering, and Product/Test teams to translate system requirements into silicon/module definitions and resolve complex silicon and packaging anomalies.
 * Packaging & Thermal Integration: Provide application-level feedback on advanced power packaging technologies, including QFN, LGA, Fan-Out Panel Level Packaging (FO-PLP), and Chip-Embedded / substrate-embedded architectures.
 * Customer Technical Advocacy: Deliver reference designs, evaluation boards (EVBs), application notes, and direct engineering support to top-tier hyperscale and server OEM/ODM hardware teams.