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# Senior RTL Design Engineer

- **Company:** Efficient Computer
- **Location:** San Francisco, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Very-Large-Scale Integration, Software Debugging, Logic Synthesis of Circuits, Data Flow Control, Reduced Instruction Set Computing, SystemVerilog, Systems Integration, Alwayson, State Machines, Power Analysis (Cryptography), Active Optical Networks, Physical Design
- **Published:** November 7, 2026
- **Apply:** https://www.juju.com/job/28_25197_ef92338b075fee9b574e3af0289f24fb-2326878604

## About the Role

* 8-10 years of front-end digital design experience on processor, accelerator, or SoC products.
 * Significant contributions to at least two tapeout cycles.
 * Strong proficiency in SystemVerilog for synthesizable RTL: state machines, arbiters, FIFOs and flow control, and datapath logic.
 * Hands-on experience with standard VLSI front-end flows: lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA, with the ability to interpret and act on their reports.
 * Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, isolation, and retention.
 * Working knowledge of at least one on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL level.
 * Experience with on-chip memories: SRAM wrappers, banking, and memory-mapped register interfaces.
 * Comfortable running RTL simulations and debugging with waveform tools.
 * Clear written and verbal communication; able to document designs and hold design reviews., * Experience designing or integrating on-chip networks, dataflow pipelines, or memory subsystems.
 * Familiarity with NVM controller RTL (MRAM, RRAM, etc.), including ECC and program/erase sequencing.
 * Experience with very low power design techniques and the RTL design choices they require.
 * Understanding of parallel execution models such as dataflow, SIMD, or systolic arrays.
 * Experience with RTL and gate-level power analysis tools and methodologies.
 * Exposure to DFT concepts: scan insertion, ATPG, and DFT-friendly RTL coding.

## Description

* Implement microarchitecture and RTL for assigned blocks in the compute fabric, on-chip networks/NoC, memory interfaces, and peripheral subsystems, working from architecture and uArch specifications.
 * Integrate third-party and in-house IP (RISC-V cores, NVM controllers, SRAM wrappers, I2S/I2C/APB peripherals) at the subsystem and SoC level, including bus fabric hookup and memory-mapped register interfaces.
 * Write and maintain uArch and design documentation for your blocks; present them in design reviews with architecture, DV, and physical design., * Own block-level front-end quality: lint-clean RTL, CDC and RDC analysis with waivers reviewed and documented, and LEC between RTL and netlist.
 * Run synthesis, write and maintain SDC timing constraints, and analyze STA reports; iterate on RTL to meet timing, area, and power targets.
 * Drive issues to closure with physical design during timing and congestion closure., * Implement low-power RTL per UPF intent: power domains, isolation, level shifters, retention, and fine-grained clock gating.
 * Contribute to PMU and always-on (AON) logic, such as power sequencing state machines and wakeup event aggregation.
 * Ensure clock-gating enables are timing-clean and CDC-correct; run RTL power analysis and act on the results., * Run block-level simulations and debug failures alongside the DV team; contribute directed test scenarios for corner cases, back-pressure, and power-state transitions.
 * Run and debug gate-level simulations.
 * Support silicon bring-up with RTL-level debug during lab validation.