> Markdown version of [/jobs/ext/4632611-asic-dft-engineer-i-full-time-united-states](https://www.wearedevelopers.com/jobs/ext/4632611-asic-dft-engineer-i-full-time-united-states). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# ASIC DFT Engineer I (Full Time) - United States

- **Company:** Cisco Systems, Inc.
- **Location:** New York, NY, United States
- **Experience:** Starter
- **Salary:** $107,800 - $157,400
- **Contract:** Internship / Graduate position
- **Skills:** Very-Large-Scale Integration, Software Debugging, Electronic Design Automation, Perl (Programming Language), Hardware Design, Joint Test Action (IEEE Standards), Python (Programming Language), Static Timing Analysis, System Testing, SystemVerilog, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, Backend, Front End Software Development, Physical Design, Software Coding
- **Published:** November 8, 2026
- **Apply:** https://diversityjobs.com/career/18876323/Asic-Dft-Engineer-I-Full-Time-United-States-California-San-Jose

## About the Role

* A Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months).

 * Qualifying education should be in ASIC DFT or a related field.

 * Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST (Built-In Self-Test, including memory BIST and boundary scan).

 * Familiarity or introductory hands-on exposure to EDA and ATPG tools along with scripting or coding skills in Python, Tcl, or Perl.

 * Experience working with gate-level simulations and debugging using simulators like VCS.

Preferred Qualifications

 * Practical experience or strong coursework in verification skills, including SystemVerilog, logic equivalency checking, and test-timing validation.

 * Understanding of basic VLSI circuit physical behaviors in silicon (such as electromigration and temperature/voltage variation effects) and familiarity with basic timing concepts (setup/hold times, metastability).

 * Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis.

 * Strong verbal and written communication skills to collaborate effectively with frontend RTL, backend physical design, and verification teams.

## Description

You will be in the Silicon One development organization as an ASIC Design for Test Engineer with a primary focus on Design-for-Test. You will work with frontend RTL teams, backend Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle. You will:

 * Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.

 * Create and enhance automation scripts to improve implementation robustness and efficiency.

 * Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.

 * Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.

 * Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.