> Markdown version of [/jobs/ext/4634392-package-integration-and-si-pi-engineer](https://www.wearedevelopers.com/jobs/ext/4634392-package-integration-and-si-pi-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Package Integration and SI/PI Engineer - **Company:** Avicenatech, Corp. - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Python (Programming Language), MATLAB, Signal Integrity, Systems Integration, Application Specific Integrated Circuits, Hfss, Model Validation - **Published:** November 8, 2026 - **Apply:** https://www.careerbuilder.com/job-details/package-integration-and-si-pi-engineer-sunnyvale-ca--4391ad5a-53fd-4362-8796-8463c83180d6 ## About the Role System Integration (SI), System Integration (SI), Receivers, ASIC (Application Specific Integrated Circuit), Link Building, Signal Integrity, Crosstalk, Analysis Skills, Thermal Analysis, Model Review, Required * MS in Electrical Engineering (or BS with equivalent experience) and 5+ years of SI/PI work on high-speed ICs and packages. * Experience with tools such as Ansys HFSS, SIwave and RedHawk, Cadence Sigrity and Clarity, or Keysight ADS. * Strong grasp of S-parameters, TDR, transmission lines and PDN design. * Flip-chip package integration experience. Preferred * 2.5D/3D or other advanced packaging. * Optical or co-packaged optics modules. * Lab measurement with VNA and oscilloscopes. * Python or MATLAB automation. Key Competencies * Systems view: thinks across die, package and board. * Analytical: grounds decisions in models and measurements. * Collaboration: bridges chip and package teams. * Clear communicator: turns analysis into concrete constraints. ## Description Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a package integration and SI/PI engineer to own the boundary between our ASIC and its package. You will make sure high-speed signals, clocks and power reach the chip cleanly, and that package constraints are reflected in the chip design early.