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# Senior Digital Design Engineer

- **Company:** NVIDIA Ltd.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $136,000 - $218,500
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Microarchitecture, Logic Synthesis of Circuits, Ethernet, Formal Verification, PCI Express, Requirements Management, AI Infrastructure, Application Specific Integrated Circuits
- **Published:** November 8, 2026
- **Apply:** https://www.careerbuilder.com/job-details/senior-digital-design-engineer-austin-tx--c8367f51-aa9f-4ee8-863f-c05d231d46d8

## About the Role

* Bachelors or Master's Degree, or equivalent experience in Electrical Engineering or Computer Engineering
 * 5+ years of relevant work experience.
 * Experience working with high-speed connectivity protocols such as NVLink, PCI-Express, Ethernet, UCIE etc.
 * Proven track record of delivering high bandwidth datapath blocks such as data movers, protocol adaptors, network-on-chip, arbiters and schedulers etc.
 * Deep understanding of ASIC design flows and methodology
 * Strong analytical and interpersonal skills, excellent teammate

## Description

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard working engineers crafting and implementing NVLink Fusion based AI infrastructure System-on-Chips. You will get a chance to create real impact in a dynamic, industry leading, technology-focused company, while working on NVLink Fusion technology. NVLink Fusion is the enabler for the next generation of standardized rack-scale AI connectivity.

What you'll be doing:

 * As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks.
 * Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean block.
 * Collaborate with chip architects, verification engineers, formal verification engineers, and SoC integration engineers in order to meet the goals of the block in a timely manner
 * Identify potential IP solutions for specific use cases and assist in selecting, customizing and integrating the right IP solutions.