> Markdown version of [/jobs/ext/4636117-principal-silicon-engineer-system-modeling](https://www.wearedevelopers.com/jobs/ext/4636117-principal-silicon-engineer-system-modeling). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Silicon Engineer - System Modeling - **Company:** Microsoft - **Location:** Redmond, WA, United States - **Experience:** Experienced - **Salary:** $142,800 - $274,800 - **Contract:** Permanent contract - **Skills:** Analog Electronics, Apple IOS, Systems Engineering, Microsoft Azure, Microsoft Online Services, Computer Engineering, Software Debugging, Perl (Programming Language), Python (Programming Language), MATLAB, Microsoft Software, Simulink, Xbox Linux, Scripting, Computer Network Operations, Control Structures, Information Technology, Search Engines - **Published:** November 8, 2026 - **Apply:** https://www.careerbuilder.com/job-details/principal-silicon-engineer-system-modeling-redmond-wa--830beb59-e521-4acc-bcf6-2a472a49c01d ## About the Role Systems Engineering, Xbox, Customer Experience, Microsoft Bing Search Engine, Network Operations Center, Microsoft Windows Azure, Sustainability, Time Management, Manufacturing, Operational Measurement, * Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience * OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience * OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience * OR equivalent experience. Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable., * MS in Electrical Engineering or PhD in Electrical Engineering * 10+ years with MS EE and 7+ years with PhD in Electrical Engineering * Experience with deep sub-micron nodes and hands on layout optimization experience * Experience Matlab (Simulink) & modeling * Understanding of Digital and analog Control loops model analysis * Post silicon validation experience in High speed IOs * Ability to review DV waveforms and debug calibration related issues * Python, Perl & other scripting languages for post silicon validation experience. * Experience running analog circuit simulations (Cadence Spectre, HSPICE) Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. ## Description * System Modeling of analog circuits & SerDes interface IP * Post Silicon interface between ATE/Validation and design teams including co-ordination of debug activities * Contribute to architectural direction and analog circuit level architecture