> Markdown version of [/jobs/ext/4639662-sr-dft-engineer-100-remote](https://www.wearedevelopers.com/jobs/ext/4639662-sr-dft-engineer-100-remote). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr DFT Engineer (100% Remote) - **Company:** Encore Semi, Inc. - **Location:** San Diego, CA, United States (Remote available) - **Experience:** Expert - **Salary:** $135,000 - $150,000 - **Contract:** Permanent contract - **Skills:** Code Coverage, Computer Engineering, Software Debugging, Perl (Programming Language), Python (Programming Language), SystemVerilog, Tcl (Programming Language), Verilog, Application Specific Integrated Circuits, Mentor Graphics - **Published:** November 8, 2026 - **Apply:** https://www.dice.com/job-detail/0e0ab8d1-48ee-4a6d-ba36-40c0eb5db879 ## About the Role * Experience: 8+ years of proven industry experience in ASIC DFT engineering. * IJTAG: Strong hands-on expertise with IEEE 1687 (IJTAG) architecture, specifically utilizing ICL and PDL formats. * DFT Tools: Deep proficiency with the Mentor Graphics (Siemens) Tessent tool suite. * Simulation: Solid simulation, verification, and debug skills using Xcelium, VCS, or QuestaSim. * Core Skills: Fluency in Verilog/SystemVerilog and strong scripting abilities (Tcl, Python, or Perl). Education: BS or MS in Electrical Engineering, Computer Engineering, or a related field. ## Description We are seeking an experienced Senior DFT Engineer to lead test architecture and implementation for complex SoCs. You will work closely with design and verification teams to drive DFT requirements from RTL through to silicon bring-up, ensuring the highest quality test coverage., * Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-generation ASIC/SoC designs. * Develop and integrate IJTAG networks across IP and SoC levels. * Perform test insertion, ATPG generation, and rigorous fault coverage analysis. * Run and debug zero-delay and timing-annotated gate-level simulations.