> Markdown version of [/jobs/ext/4640236-hardware-design-architect](https://www.wearedevelopers.com/jobs/ext/4640236-hardware-design-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Hardware Design Architect - **Company:** FAST Service Tech LLC - **Location:** San Diego, CA, United States - **Contract:** Permanent contract - **Skills:** Board Bringup, Artificial Intelligence, Logic Synthesis of Circuits, Microprocessors, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Hardware Design, PCI Express, Systems Architecture, Graphics Processing Unit (GPU), Hardware Infrastructure - **Published:** November 8, 2026 - **Apply:** https://www.careerbuilder.com/job-details/hardware-design-architect-san-diego-ca--1738f061-eda0-4e2c-b036-40ffdadab121 ## About the Role Hardware Design, Hardware Architecture, Hardware Design, Hardware Architecture, Systems Hardware, Embedded Systems, System Architecture, Embedded Hardware, FPGA, CPU (Central Processing Unit) ## Description Architect complex hardware - 5G radios, AI and NPU accelerator systems, edge compute - where FPGAs, AI accelerators, CPUs and GPUs have to work together on a board, inside real power, thermal and signal-integrity limits. Full time12+ yearsBengaluru, India ยท United States THE WORK What the role involves. * Own the board and system architecture for complex hardware - 5G radio units, AI and NPU accelerator systems, edge compute - partitioning the design across FPGA, accelerator, CPU and GPU. * Choose the devices and interfaces - SoCs, FPGAs, AI accelerators, memory, SerDes, PCIe, DDR, Ethernet - and own the high-speed digital design and the signal and power integrity. * Set the power, thermal and cost budgets, and own the trade-offs between them and performance. * Drive the design from architecture through schematic, layout review and board bring-up, with the firmware and silicon teams. * Stand in front of customers on the hard system-level calls, and set the hardware sign-off criteria. Hardware architectureHigh-speed digitalFPGAAI / NPU acceleratorsSoC / CPU / GPUSignal & power integrity