> Markdown version of [/jobs/ext/4640891-fpga-development-lead-level-4](https://www.wearedevelopers.com/jobs/ext/4640891-fpga-development-lead-level-4). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# FPGA Development Lead (level 4)

- **Company:** Firefly Aerospace
- **Location:** Cedar Park, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Systems Engineering, Command-Line Interface, Computer Engineering, Software Debugging, Embedded Software, Ethernet, Formal Verification, Field-Programmable Gate Array (FPGA), Hardware Design, Python (Programming Language), PCI Express, Static Timing Analysis, SystemVerilog, Systems Integration, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Fpga Hardware, Physical Design
- **Published:** November 8, 2026
- **Apply:** https://www.careerbuilder.com/job-details/fpga-development-lead-level-4-cedar-park-tx--38bfefe7-575c-4eb2-8472-38aec0df0cee

## About the Role

FPGA, Government, Aerospace and Defense, Technical Leadership, FPGA Design, FPGA, High Reliability, RTL Design, Best Practices, Timing Verification, Required

 * Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
 * Minimum 8+ years of FPGA development experience.
 * Strong proficiency in VHDL and/or Verilog/SystemVerilog for RTL design.
 * Experience with FPGA architectures (e.g., AMD/Xilinx, Intel/Altera, or similar) including timing closure, place-and-route, and constraints.
 * Hands-on experience with FPGA lab bring-up, debugging, and integration with embedded systems or hardware.
 * Demonstrated ability to mentor or technically lead other engineers (formal people management not required).
 * Ability to work in a dynamic environment with changing needs and requirements.
 * Team player with a can-do attitude; comfortable contributing both independently and collaboratively.
 * Enjoys being challenged and learning new skills.
 * Excellent written and verbal communication skills.

Desired

 * Master's degree in Electrical Engineering, Computer Engineering, or related field.
 * Experience with high-speed interfaces (SERDES, PCIe, Ethernet, DDR, SpaceWire, or similar).
 * Familiarity with radiation-tolerant or space-qualified FPGA devices and SEU mitigation techniques.
 * Experience with verification methodologies (UVM, constrained-random testing, formal verification, or similar).
 * Integration experience with SoCs, embedded processors, or mixed-signal systems.
 * Exposure to synthesis, static timing analysis, and power/thermal considerations for flight hardware.
 * Comfortable with scripts and command-line tools (Tcl, Python, etc.).
 * Prior experience in aerospace, space systems, or other high-reliability domains.

## Description

As the FPGA Development Lead, you will play a pivotal role in shaping the future of Firefly Aerospace and space exploration. You will serve as a senior technical leader and hands-on contributor, designing, implementing, and verifying high-reliability FPGA designs for our launch vehicles, spacecraft, and ground systems.

You will provide technical direction, mentor engineers on complex FPGA problems, and drive best practices while remaining deeply involved in RTL design, verification, timing closure, and hardware integration. This role requires strong technical depth in FPGA development for aerospace applications, the ability to influence and elevate the work of others, and a deep passion for space exploration.

You will partner closely with embedded software, hardware, GNC, and systems engineering leads to ensure high-quality, reliable FPGA solutions and continuous improvement of our development approach. Candidates should be prepared for a fast-paced startup environment. This position requires high levels of creativity, flexibility, technical ownership, and collaboration. The ability to communicate effectively within a multi-disciplinary and multi-cultural group is a must.

Responsibilities

 * Technical Leadership & Mentorship: Provide technical direction and guidance to FPGA engineers. Mentor teammates on architecture, RTL design, verification strategies, timing closure, and debugging. Help grow the technical capability of the team through knowledge sharing, design reviews, and hands-on collaboration.
 * Technical Excellence: Drive adoption of best practices in FPGA development, reliability, and design verification. Act as a lead contributor to the architecture, RTL implementation, and verification of high-reliability FPGA designs.
 * Hands-on Development: Own significant portions of FPGA designs from concept through implementation, timing closure, lab bring-up, integration, and verification. Contribute directly to RTL coding, constraint development, simulation, and problem resolution.
 * Process Improvement: Help establish and refine clear FPGA development processes for design, verification, timing analysis, and integration that the team can effectively apply.
 * Collaboration & Integration: Work closely with embedded software, hardware engineering, systems engineering, and other stakeholders to ensure seamless integration of FPGA designs with overall avionics and vehicle systems.