> Markdown version of [/jobs/ext/4647750-senior-staff-asic-platform-engineer](https://www.wearedevelopers.com/jobs/ext/4647750-senior-staff-asic-platform-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Staff ASIC Platform Engineer - **Company:** SanDisk - **Location:** Longmont, CO, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Software Debugging, Linux, Firmware, Field-Programmable Gate Array (FPGA), Joint Test Action (IEEE Standards), PCI Express, SAP Sales and Distribution, Tcl (Programming Language), Universal Asynchronous Receiver/Transmitter, Application Specific Integrated Circuits - **Published:** November 9, 2026 - **Apply:** https://www.thejobnetwork.com/job/00944a7e-e0ed-4ef4-b96f-dd282e10bc08/senior-staff-asic-platform-engineer ## About the Role The ideal candidate brings broad system-level knowledge with depth in one or more areas such as pre-silicon emulation, FPGA prototyping, ASIC validation, firmware enablement, automation, or platform engineering. Success in this role requires the ability to understand complex development workflows, solve difficult cross-layer technical problems, and translate those solutions into reliable and reusable platforms that can operate at scale., * Expertise with Cadence, Siemens and/or Synopsys emulation platforms or FPGA-based prototyping environments \n * Ability to debug complex system-level issues across hardware, software, and platform infrastructure \n * Familiarity with host interfaces such as PCIe, UFS, USB, and SD \n * Familiarity with peripheral interfaces such as UART, JTAG, I2C, HSSTP, and related protocols. \n * Experience working in Linux and Windows environments \n * Expertise in Tcl \n * Experience supporting pre-silicon development in cross-functional teams and optimizing hardware usage at scale \n * Understanding of firmware development process and how that intersects with ASIC development and FPGA design \n