> Markdown version of [/jobs/ext/4648590-asic-design-verification-engineer-security-group-sr-staff](https://www.wearedevelopers.com/jobs/ext/4648590-asic-design-verification-engineer-security-group-sr-staff). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Design Verification Engineer [Security Group] - Sr Staff - **Company:** ANS Electric LLC - **Location:** Santa Clara, CA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Microarchitecture, Software Debugging, Perl (Programming Language), Python (Programming Language), Reduced Instruction Set Computing, Software Requirements Analysis, Unix Commands, Application Specific Integrated Circuits - **Published:** November 9, 2026 - **Apply:** https://www.juju.com/job/28_25197_a7c5ae88516a70f979b59874798aa316 ## About the Role * Minimum 10 years of SOC-level verification experience. * Strong understanding of ARM-based or RISC-V processors and APB/AHB/AXI protocols. * Solid grasp of SV/UVM concepts and cryptographic algorithms preferred. * Basic knowledge of UNIX commands and Python/Perl scripting. * ASIC Design Services * Verification * Packaging & Wafer * Semiconductor IP * ASIC Design Services * Verification * Packaging & Wafer * Semiconductor IP ## Description Qualcomm is seeking a Hardware Engineer to drive innovation in electronic systems design and verification. This role involves collaborating with cross-functional teams to develop and validate cutting-edge products, ensuring they meet performance standards and are ready for market launch., * Collaborate with subsystem and SOC Architects to understand high-level system requirements. * Develop detailed Test and Coverage plans based on architecture and micro-architecture. * Create Verification Methodology for scalability and portability across environments. * Build Verification environments including Stimulus, Checkers, Monitors, Assertions, and Coverpoints. * Execute Verification Plans, including Design Bring-up and Debug of test failures. * Track and report DV progress using various metrics.