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# Principal Engineer, System HW Design - SI/PI

- **Company:** DEWINTER, INC.
- **Location:** San Jose, CA, United States
- **Contract:** Temporary to permanent
- **Skills:** Gigabit Ethernet, Artificial Intelligence, Software Debugging, Digital Technology, Electronic Design Automation, Firmware, Network Architecture, PCI Express, Signal Integrity, Graphics Processing Unit (GPU), Application Specific Integrated Circuits, Hfss, Nvme
- **Published:** November 9, 2026
- **Apply:** https://www.juju.com/job/28_25197_12bb007949f725df6335bc4c3c4208db

## About the Role

* Bachelor's degree in Electrical Engineering or a related field.
 * Approximately 15 years of industry experience in signal integrity and power integrity engineering for high-speed digital systems.
 * Experience leading SI/PI strategy across multiple concurrent hardware programs.
 * Deep expertise with:
 * PCIe Gen4/Gen5, including PCIe Gen5 operation up to 32 GT/s per lane.
 * DDR4, DDR5, and LPDDR memory channels.
 * USB 3.x and USB Type-C.
 * MIPI D-PHY and C-PHY.
 * 10 Gigabit Ethernet SerDes.
 * Proven experience driving high-speed interface margin closure on production designs.
 * Track record owning power delivery network architecture for high-power SoCs, ASICs, AI accelerators, GPUs, or comparable compute silicon.
 * Expert proficiency with SI/PI EDA tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Keysight ADS, or equivalent platforms.
 * Experience selecting SI/PI tools and developing reusable simulation methodologies.
 * Extensive hands-on lab validation experience using VNAs, TDRs, and high-bandwidth oscilloscopes.
 * Experience owning escalation-level SI/PI debug.
 * Expertise in PCB stack-up design, impedance control, transmission line theory, S-parameters, and channel modeling.
 * Strong working knowledge of PCIe-SIG, USB-IF, and MIPI Alliance compliance standards.
 * Ability to define technical direction, establish engineering standards, and mentor senior- and staff-level engineers.
 * Strong cross-functional leadership skills, with the ability to align ASIC, package, hardware, layout, and firmware teams.
 * Proactive, solutions-oriented approach with a strong sense of ownership and accountability.
 * Excellent verbal and written communication skills, including the ability to explain complex technical concepts to diverse audiences., * Master's degree in Electrical Engineering or a related field.
 * Knowledge of ASIC characterization, PCB manufacturing, assembly, test, quality, and reliability.
 * Experience supporting or owning PCIe-SIG, USB-IF, or MIPI Alliance compliance testing.
 * Experience defining connector and interconnect strategies across multiple product generations.
 * Experience working with board-to-board, M.2 NVMe, and PCIe edge-card interfaces.
 * Experience engaging with component and module vendors or industry standards organizations.
 * A record of delivering complex technical programs in ambiguous, fast-moving environments.
 * Creative and intellectually curious approach to solving challenging hardware problems.

Preferred Education and Experience

 * Bachelor's degree in Electrical Engineering or a related discipline required.
 * Master's degree preferred.
 * Approximately 15 years of professional experience in SI/PI engineering for high-speed digital systems preferred.
 * Demonstrated experience providing product-line-level technical leadership across multiple board programs., * Ability to work collaboratively across internal engineering teams and external vendors.
 * Ability to drive long-term SI/PI architecture, methodology, and standards while remaining hands-on with design, simulation, validation, and debug.

## Description

This is a high-impact technical leadership role for an engineer who can establish organization-wide SI/PI standards, guide complex board designs, close high-speed interface margins, and solve the most challenging lab validation and bring-up issues. You will work across ASIC, package, hardware, layout, firmware, manufacturing, and external vendor teams to deliver reliable high-speed signaling and power delivery for advanced compute systems.