> Markdown version of [/jobs/ext/4651225-digital-verification-engineer](https://www.wearedevelopers.com/jobs/ext/4651225-digital-verification-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Digital Verification Engineer

- **Company:** Nuevo
- **Location:** Barcelona, Spain
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Software Debugging, Perl (Programming Language), Firmware, Python (Programming Language), Regression Analysis, Perforce, Performance Tuning, SystemVerilog, Tcl (Programming Language), Application Specific Integrated Circuits, Fpga Hardware, Git, Physical Verification
- **Published:** November 10, 2026
- **Apply:** https://www.adzuna.es/details/5959687174

## About the Role

This is a technical execution role requiring independent problem solving, ownership of verification tasks and collaboration with RTL, architecture and firmware teams., * 5+ years in ASIC/SoC functional verification.

 * Recent DDR/LPDDR or comparable high speed protocol verification experience.
 * Knowledge of AMBA protocols, including AXI, AHB, CHI or CXS.
 * Strong SystemVerilog, UVM and coverage closure experience.
 * Experience with VCS, Xcelium or Questa.
 * Good RTL debugging and SoC architecture knowledge.
 * Independent problem solving and verification task ownership.
 * Relevant engineering degree.

Important: Direct ASIC/SoC functional verification experience, including UVM development, protocol verification and coverage closure, is essential. RTL design, FPGA development or physical verification alone is insufficient.
Optional / Desired

 * Python, Perl or TCL scripting.
 * Git, Perforce, LSF or Grid Engine.
 * AI tools for verification and regression analysis.
 * Simulation performance optimization.
 * Strong documentation and communication skills.

## Description

You will develop and maintain SystemVerilog/UVM testbenches, debug protocol issues and drive coverage closure, ensuring functional correctness and compliance., * Perform functional verification of DDR/LPDDR interfaces at IP and subsystem levels.

 * Develop and maintain SystemVerilog/UVM testbenches.
 * Verify DDR/LPDDR and AMBA protocol compliance.
 * Debug RTL, verification model and specification mismatches.
 * Execute regressions, investigate failures and drive bug closure.
 * Contribute to functional coverage and verification signoff.
 * Optimize simulation performance and automate verification workflows.
 * Collaborate with RTL, architecture and firmware teams.
 * Maintain verification documentation and methodologies.