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# Senior Digital Verification Engineer

- **Company:** Cadence Design Systems
- **Location:** Cesson-Sévigné, France (Remote available)
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Bash Shell, Code Coverage, Profiling, Computer Engineering, Software Debugging, Formal Verification, Field-Programmable Gate Array (FPGA), Make (Software), Python (Programming Language), SystemVerilog, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, Git
- **Published:** November 10, 2026
- **Apply:** https://dejobs.org/x/x/AE838FC44D74468E886384A061570150/job/

## About the Role

* B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
 * 7 - 10 years of professional digital verification experience, including 5 years with UVM on ASIC or FPGA projects
 * Proficiency in SystemVerilog/UVM
 * Strong hands - on experience with Cadence Xcelium
 * Knowledge of synthesis - aware verification (e.g., constraint - driven random verification, coverage - driven closure)
 * Deep understanding of functional coverage, assertions (SVA), formal verification, and constrained - random verification
 * Comfortable with large - scale simulation environments, waveform analysis, and performance profiling
 * Excellent communication, problem - solving, and leadership capabilities
 * Ability to influence cross - functional teams and mentor junior engineers.
Additional Skills/Preferences:

 * Hands - on with verification IP (VIP) development and integration
 * Exposure to low - power verification (e.g., power - aware UVM, clock gating checks)
 * Scripting in Python, TCL, Makefile or Bash for automation
 * Familiarity with Git and CI/CD tools

## Description

You will lead the development and execution of robust, reusable UVM verification environments for our products, ensuring functional - coverage and first - silicon success.

By driving verification strategy, automating large - scale regression flows, and mentoring the verification team, the role directly safeguards the quality of high - performance ASIC designs.

The work spans building scalable test - bench architectures, integrating Cadence verification tools, and collaborating cross - functionally with design and software teams to close verification gaps before RTL freeze.
Job Responsibilities:

 * Define and implement robust, scalable UVM test - bench architectures for complex digital IPs
 * Create and maintain reusable verification components (sequencers, drivers, monitors, scoreboards, coverage models)
 * Develop directed, random, and constrained - random test cases to achieve 100 % functional coverage and 100 % code coverage on target designs
 * Lead root - cause analysis of simulation failures, performance bottlenecks, and silicon bring - up bugs
 * Coordinate with design teams to close verification gaps before RTL freeze
 * Contribute to internal verification guidelines, templates, and training materials
 * Mentor junior verification engineers (T1 - T3) and provide technical guidance on UVM, test - bench design, and debugging techniques
 * Participate in design/verification reviews, providing constructive feedback and risk assessment