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# Staff DFT Design Engineer

- **Company:** Openchip & Software Technologies
- **Location:** Barcelona, Spain
- **Contract:** Permanent contract
- **Skills:** Logic Synthesis of Circuits, Perl (Programming Language), Make (Software), Python (Programming Language), Tcl (Programming Language), Scripting
- **Published:** November 11, 2026
- **Apply:** https://www.adzuna.es/details/5960634224

## About the Role

BSc/MSc in Electrical/Electronic Engineering (or in a related field) with 10+ years of experience gained in IC digital design with multiple cycles of DFT and RTL design. Good knowledge of MBIST Insertion, Compression Insertion, Scan Stitching, OCC insertion, iJTAG. Good Knowledge of ATPG, Pattern Generation, Simulation. Understanding of basic commands of EDA/Simulation tools, e.g. Tessent, VCS Hands on Experience in DFT Flow bring up using scripting languages like TCL/Perl/Makefile based. Hands on Experience in flow bring up for MBIST Insertion, EDT/OCC insertion, Scan Stitching, ATPG/Simulation Flow. Hands on Exp in scripting languages: TCL, Perl., Experience working in a large corporation. Knowledge of Network on chip architecture. RiscV ISA/architecture and SOC based on this processor. Knowledge of high level (architecture) digital design language. Knowledge of architecture analysis tools used for metric analysis. Good knowledge of scripting languages: Perl, Python., We are looking for team players that focus on the outcome of the team above the individual needs, with respect and honest challenge. Within- and cross-team collaboration at the technical level. The ideal candidate should count with a "can do attitude", willing to solve any obstacle by himself. Self-starter and self-motivated.

## Description

Work on design execution of silicon design. Work on SoC DFT architecture and DFM concept. Work on the implementation and verification of DFT measures to meet product specifications and production requirements. Work closely with cross-function teams (design, production test and qualification) to meet test requirements with effective DFT solutions. Contribute to target coverage requirements for logic, memories, IO and mixed-signal IPs. Generate test patterns and support post-silicon ATE and QnR.