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# Senior SoC Integration Engineer

- **Company:** Lattice Semiconductor
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Bash Shell, Logic Synthesis of Circuits, Electronic Design Automation, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Internet Protocol, Python (Programming Language), System on a Chip, SystemVerilog, Systems Integration, Tcl (Programming Language), Test Data, Verilog, Application Specific Integrated Circuits, Physical Design
- **Published:** November 11, 2026
- **Apply:** https://www.careerbuilder.com/job-details/senior-soc-integration-engineer-san-jose-ca--9a8ff51d-3ce3-46d6-9976-6b8de485ccc9

## About the Role

System Integration (SI), System-on-a-Chip (SoC), Sales, Marketing, Customer Support/Service, Research & Development (R&D), Manufacturing Operations, Semiconductors, Design Flows, IP (Internet Protocol), * BS or MS in Electronics, Computer, or Electrical Engineering, with 10+ years of experience in ASIC, SoC, or FPGA design and product development.

 * Proven expertise in both custom and digital design implementation for IP and full-chip integration, including RTL coding (Verilog/System Verilog), synthesis, equivalence checking, SDC/STA, and DFT/ATPG flows.

 * Familiarity with custom design concepts: transistor-level analysis and circuit characterization and power simulation using industry-standard EDA tools.

 * Working knowledge of circuit-level power simulation, CMOS low-power design concepts, and correlating simulated results to silicon/bench measurement data across multiple process nodes/foundries.

 * Strong scripting ability (e.g., Python, Perl, TCL, Shell) and excellent communication skills to work across design, test, and product engineering teams; project leadership and product development cycle experience (planning, tapeout, silicon validation) is a plus.

## Description

The position is for a Senior SoC Integration Engineer at Lattice Semiconductor. The engineer will be part of the Silicon Integration Team, responsible for integrating IP blocks into the full chip using both digital and custom design flows, while also contributing to full-chip power modeling and silicon correlation in support of other engineering teams., * Integrate IP blocks - including DDR PHY - into the full chip using both digital and custom design flows: developing RTL, synthesis, timing constraints (SDC), and timing closure (STA) across multiple IP sources, and resolving DFT integration issues with IP and product teams. Deliver the resulting models, views, and collateral needed for other engineering teams to sign off.

 * Support custom and physical design integration tasks, including custom cell design and reuse across the chip, parasitic extraction, and clock-critical signal routing and shielding review ahead of tapeout.

 * Collaborate with IP design, product engineering, and test teams on full-chip power modeling: validating current and power assumptions per supply domain, reviewing circuit- and physical-design power simulation results, and correlating simulated power models to silicon bench and production test data to support test screen definition.