> Markdown version of [/jobs/ext/4681844-senior-soc-performance-analysis-engineer-210716](https://www.wearedevelopers.com/jobs/ext/4681844-senior-soc-performance-analysis-engineer-210716). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior SoC Performance Analysis Engineer - 210716 - **Company:** GDKN Corporation - **Location:** Phoenix, AZ, United States - **Experience:** Expert - **Contract:** Temporary contract - **Skills:** Microarchitecture, Multiprocessing, Performance Tuning, Application Specific Integrated Circuits, Information Technology, Performance Monitor - **Published:** November 12, 2026 - **Apply:** https://www.thejobnetwork.com/job/fdaaca18-0174-42d1-809c-bdf92d5d078c/senior-soc-performance-analysis-engineer- ## About the Role * 8+ years of experience in SoC performance analysis. * Hands-on experience with LLC, L2/L3 cache, NoC, and memory controllers. * Strong knowledge of Intel PMU, uncore counters, Intel PCM, CAT, MBA, and RDT. * Experience with bandwidth allocation, QoS enforcement, and latency characterization. * Experience with Intel CPU architecture or performance engineering teams. * Bachelor's degree in Engineering, Computer Science, or a related field. * AC20-193 certification experience preferred/required as confirmed by client. ## Description We are seeking an experienced SoC Performance Analysis Engineer to develop performance-monitoring tools and analyze CPU cache, memory bandwidth, and on-chip interconnect performance. The ideal candidate will have strong experience with Intel processor architectures, PMU counters, cache characterization, and QoS optimization., * Develop automated performance-monitoring tools using Intel PMU and uncore counters. * Analyze L2/L3 cache, LLC occupancy, memory bandwidth, and inter-core interference. * Monitor NoC traffic, throughput, latency, and cache contention. * Establish bandwidth allocation, QoS limits, and channel priorities. * Perform performance analysis on Intel Tiger Lake, Ice Lake, Alder Lake, and Xeon platforms. * Support performance optimization, testing, documentation, and cross-functional engineering teams. Preferred Background: Intel CPU Architecture, Intel Platform Enablement, Hyperscaler Performance Engineering, Xeon QoS/RDT, Networking ASIC, or Automotive Multicore Engineering.