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# Lead Software Engineer - HYBRID

- **Company:** STRUCTURES COMPANY LLC
- **Location:** Phoenix, AZ, United States
- **Experience:** Expert
- **Salary:** $291,200
- **Contract:** Temporary to permanent
- **Skills:** Software Applications, Computer Programming, Network Layer, Software Engineering, System on a Chip, Performance Monitor
- **Published:** November 12, 2026
- **Apply:** https://www.careerbuilder.com/job-details/lead-software-engineer-hybrid-phoenix-az--95d8fbd2-4df1-48ab-b68b-aff711a57250

## About the Role

Software Engineering, Software Engineering, Aerospace and Defense, Recruiting/Staffing Agency, United States Citizen, Regulations, System-on-a-Chip (SoC), Machine Tool, Performance Analysis, Layer 3 Protocols, * Must be a U.S. Person (as defined by ITAR).

 * 8+ years of SoC analysis experience associated with building tooling or processes around performance monitoring.
 * Experience monitoring usage, throughput, and collisions of traffic through L2/L3 cache and network-on-chip or communication fabric between on-die elements.
 * Ability to characterize and establish limits for bandwidth allocation, QoS values, channel priorities, and similar related technologies.
 * Experience with Intel TigerLake, IceLake, or AlderLake chips.
 * AC20-193 certification experience.
 * Experience developing tooling to monitor LLC occupancy, memory-controller bandwidth utilization, and inter-core interference using Intel PMU/uncore counters.
 * Experience characterizing worst-case latency effects of cache and fabric contention and establishing QoS/bandwidth-allocation limits.
 * Experience creating automated performance-monitoring infrastructure for Intel Xeon/Tiger Lake platforms to track cache misses, memory traffic, and QoS effectiveness.
 * Bachelor's degree in a related area and 6-8 years of experience in the field., Must be a U.S. Person (U.S. citizen, lawful permanent resident, or protected individual under 8 U.S.C. 1324b(a)(3)) to comply with ITAR regulations.

Keywords: aerospace, aviation, engineering, maintenance, aircraft design, defense

## Description

* Builds tooling and processes around SoC performance monitoring.
 * Monitors usage, throughput, and collisions of traffic through L2/L3 cache and network-on-chip or communication fabric between on-die elements.
 * Characterizes and establishes limits for bandwidth allocation, QoS values, channel priorities, and related technologies.
 * Develops tooling to monitor LLC occupancy, memory-controller bandwidth utilization, and inter-core interference using Intel PMU/uncore counters.
 * Characterizes worst-case latency effects of cache and fabric contention and establishes QoS/bandwidth-allocation limits for mixed-criticality workloads.
 * Creates automated performance-monitoring infrastructure for Intel Xeon/Tiger Lake platforms to track cache misses, memory traffic, and QoS effectiveness.
 * Applies Intel TigerLake/IceLake/AlderLake chip experience and AC20-193 certification experience.
 * Designs, modifies, develops, writes, and implements software programming applications.
 * Supports and installs software applications or operating systems and participates in test review, analysis, witnessing, and certification.