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# Timing/Power Methodology Architect

- **Company:** Advanced Micro Devices, Inc.
- **Location:** Sunset Valley, TX, United States
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Artificial Intelligence, Data Analysis, Perl (Programming Language), Internet Protocol, Python (Programming Language), Supercomputing, Tcl (Programming Language), Scripting, Graphics Processing Unit (GPU), Physical Design
- **Published:** November 12, 2026
- **Apply:** https://www.careerbuilder.com/job-details/timing-power-methodology-architect-austin-tx--ddec35b6-dfbf-45bc-95aa-a0611dfa9ca0

## About the Role

Healthcare, Artificial Intelligence (AI), Low Power, Graphics, Detail Oriented, Cross-Functional, Problem Solving Skills, Design Flows, IP (Internet Protocol), Budgeting, In this multi-functional role, you will have the opportunity to work across multiple divisions to drive physical design methodology optimizations across the entire physical design space (library/technology/flows/design). We're looking for someone with excellent attention to detail, passion and curiosity to resolve complex issues while achieving amazing results!, Expertise in these topics would be a plus:

 * Design experience in sub-micron processes
 * Familiarity with CPU and or GPU architecture
 * Hands-on experience with power-analysis and measurement tools like Prime Power and or Power-Artist
 * Experience with high-performance clocking
 * STA methodologies for timing closure, OCV and other advanced statistical margining techniques
 * Proficiency in scripting languages such as Perl/Tcl/Python
 * Proficiency in data analysis and interpretation

ACADEMIC CREDENTIALS:

 * MS/PhD degree in Electrical Engineering is preferred
 * Mastery of logic, circuit design, and CAD tools for high-performance design is expected

## Description

Are you passionate about pushing the boundaries of power efficiency and high-frequency computing? As a part of our AMD physical design methodology team, you can help define timing, power, and clocking methodologies for our next-generation, high-performance cores, graphics and machine intelligence chips. This team collaborates across AMD, working on projects ranging from low power APUs to the world's most powerful supercomputers., Responsibilities may include a subset of the following topics:

 * Drive PVT corners/ frequency targets while considering various product performance modes and guard bands
 * Drive IP physical implementation recipes from synthesis to route to achieve the best performance/watt
 * RTL (architecture) and PD co-development to identify bottlenecks
 * Drive budgeting, measurement, analysis and tracking of power-consumption
 * Establish global methodologies and best-known physical implementation recipes for optimal performance/watt across library/flow/Synthesis/P&R environment
 * Drive best practices for global/local clock distribution methodologies including skew/power/jitter trade-off's
 * Create guidelines on clocking/timing/power sign-off methodologies, AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.