> Markdown version of [/jobs/ext/4690854-physical-ai-soc-architect](https://www.wearedevelopers.com/jobs/ext/4690854-physical-ai-soc-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Physical AI SoC Architect - **Company:** Advanced Micro Devices, Inc. - **Location:** San Jose, CA, United States - **Salary:** $200,000 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Computer Vision, C++ (Programming Language), Computer Engineering, Extract Transform Load (ETL), Data Flow Control, Python (Programming Language), MATLAB, Machine Learning, Reduced Instruction Set Computing, Signal Processing, Data Streaming, SystemC, Network Switches, Graphics Processing Unit (GPU), Information Technology, Low Latency, Machine Learning Operations - **Published:** November 12, 2026 - **Apply:** https://diversityjobs.com/career/18905580/Physical-Ai-Soc-Architect-California-San-Jose ## About the Role You are passionate about System and SoC architecture and understand how workload characteristics translate into silicon requirements. You combine strong analytical and performance-modeling skills with knowledge of heterogeneous SoCs, processors, AI acceleration, memory systems, and interconnects. You bring broad system-level understanding along with depth in one or more areas such as AI/ML, automotive, robotics, multimedia/imaging, GPU, signal processing, or power/performance. You enjoy solving complex system-level problems and collaborating across hardware, software, performance, and customer-facing teams., * Strong experience with heterogeneous SoC architecture and system performance analysis. * Knowledge of x86 and/or ARM or RISC-V processor architecture, cache/memory hierarchies, coherent interconnects, and heterogeneous acceleration. * Experience with AI/ML inference, computer vision, robotics, automotive, multimedia/imaging, or other complex SoC workloads. * Strong understanding of DDR/LPDDR, cache and memory behavior, NoC/interconnect traffic, latency, QoS, and data movement. * Experience developing analytical or simulation-based performance models using Python, C/C++, SystemC, MATLAB, or similar tools. * Ability to translate application workloads into quantitative architecture requirements and identify system performance bottlenecks. * Experience contributing to architecture, design, verification, or implementation across the SoC development lifecycle is highly valued. * Familiarity with embedded system constraints including power, thermal limits, real-time performance, functional safety, and security is a plus. ACADEMIC CREDENTIALS * BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. ## Description We are seeking an experienced SoC Architect to define next-generation SoCs for automotive, robotics, vision, and Physical AI applications. In this role, you will define SoC architecture and translate real-world workloads and customer use cases into quantitative SoC requirements spanning compute, memory, bandwidth, interconnect, data movement, power, and end-to-end latency. You will work across the SoC development lifecycle, evaluating architectural alternatives and helping translate system-level requirements into executable SoC designs. THE PERSON, * Translate Physical AI, automotive, robotics, and vision workloads into SoC compute, memory, bandwidth, interconnect, and latency requirements. * Model end-to-end data flows across sensor, CPU, AI accelerators, memory hierarchy, on-chip interconnect, and I/O. * Analyze and optimize data placement and movement across DDR memory, caches, on-chip memory, accelerator-local memory, and buffers. * Correlate AI compute requirements and accelerator performance with memory bandwidth, data movement, utilization, and system-level performance. * Perform what-if and scaling analyses across camera count, resolution, frame rate, AI model characteristics, precision, memory configuration, and accelerator performance. * Develop data-flow diagrams, bandwidth models, traffic timelines, latency budgets, and bottleneck analyses to drive architecture decisions. * Evaluate architectural alternatives and make informed performance, power, area, and cost trade-offs. * Collaborate with SoC, AI, CPU, memory, interconnect, software, and performance teams to optimize end-to-end system performance. * Support architectural decisions through implementation and execution across the SoC development lifecycle., AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.