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# VLSI ASIC Verification Engineer

- **Company:** Broadcom
- **Location:** Mendota Heights, MN, United States
- **Experience:** Expert
- **Salary:** $109,700 - $175,500
- **Contract:** Permanent contract
- **Skills:** Very-Large-Scale Integration, Code Coverage, Computer Engineering, Software Debugging, Electronic Design Automation, Perl (Programming Language), Serial ATA, Formal Verification, Python (Programming Language), Regression Analysis, PCI Express, Reduced Instruction Set Computing, SAS (Software), Subsystems, SystemVerilog, Tcl (Programming Language), Virtual Memory, Scripting, Application Specific Integrated Circuits, Caching, Build Management, Nvme
- **Published:** November 12, 2026
- **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-Mendota-Heights-Northland/VLSI-ASIC-Verification-Engineer_R027765

## About the Role

We are looking for a detail-oriented and experienced VLSI ASIC Verification Engineer to join our silicon engineering team. In this role, you will own the functional verification of complex digital blocks and subsystems. You will build scalable, reusable UVM testbenches, drive constrained-random and assertion-based verification, and ensure zero-bug tape-outs., * Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.

 * Experience: minimum 8 years of hands-on experience in ASIC, SoC, or IP design verification.
 * Core Methodologies: Deep proficiency in SystemVerilog and UVM architectures (agents, drivers, monitors, scoreboards, virtual sequences).
 * Bus Protocols: Solid working knowledge of AMBA protocols (AXI, AHB, APB) and memory/DMA controllers.
 * Verification Techniques: Proven track record in constrained-random verification, functional coverage closure, and assertion-based verification (SVA).
 * EDA Tools: Hands-on experience with industry-standard simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium/Incisive, Mentor/Siemens Questa, or Verdi).
 * Scripting: Strong scripting skills (Ex: Python, Tcl, or Perl) for build-flow automation and regression management., * Familiarity with formal verification tools and techniques.
 * Processor Architectures: Hands-on verification experience with RISC-V, ARM, or x86 core or subsystem architectures.
 * CPU Pipeline & Core Verification: Deep understanding of processor pipelines, branch prediction, out-of-order execution, superscalar designs, and execution units (ALU/FPU).
 * Memory Subsystem Expertise: Familiarity with verifying complex memory hierarchies, including L1/L2 caches, cache coherency protocols (AMBA CHI / ACE), MMUs, and virtual memory management.
 * Exposure to high-speed interfaces or external protocols (DDR, PCIe, NVMe, SATA, or SAS).

## Description

* Verification Planning: Analyze micro-architectural specifications to create comprehensive verification plans, trace requirements, and identify edge/corner cases.
 * Testbench Development: Design and build modular, reusable verification environments and testbenches using SystemVerilog and Universal Verification Methodology (UVM).
 * Stimulus & Scoreboarding: Develop constrained-random stimulus, functional coverage models, scoreboards, and reference models.
 * Assertions & Debug: Write SystemVerilog Assertions (SVA) to catch design violations early, run simulations, debug waveforms, and root-cause RTL-to-testbench mismatches.
 * Coverage Closure: Drive functional and code coverage to 100% closure prior to tape-out.
 * Automation & Regressions: Maintain automated regression suites using scripting languages like Python, Perl, or Tcl.