> Markdown version of [/jobs/ext/4704404-xpu-architect](https://www.wearedevelopers.com/jobs/ext/4704404-xpu-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # XPU Architect - **Company:** VOLANTIS SEMICONDUCTOR, INC. - **Location:** Austin, TX, United States - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Microprocessors, Internet Protocol, Network Switches, Application Specific Integrated Circuits, Low Latency, Model Inference - **Published:** November 13, 2026 - **Apply:** https://www.careerbuilder.com/job-details/xpu-architect-austin-tx--80181988-5d36-490d-9ae8-63ce348c2e40 ## About the Role Memory Hardware, IP (Internet Protocol), Computer Architecture, ASIC (Application Specific Integrated Circuit), Artificial Intelligence (AI), CPU (Central Processing Unit), Network Switching, Architectural Services, We're looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a creative way to solve the bandwidth demand challenges and memory system interface challenges. Future generations of the compute XPU will be semi-custom and custom designs., * Previous experience architecting and owning a high performance, high TDP ASIC (eg AI chips, network switch chips, high performance CPUs or similar) * Knowledge of both computer architecture but also silicon implementation, and understanding of the realistic constraints that silicon implementation places upon architectural options * Deep understanding of AI workloads, especially low latency LLM inference * Understanding of workload and system level bottlenecks, especially around inference, as it pertains to interconnect, memory capacity, bandwidth, latency, etc. Strongly Preferred: * Hands-on experience with AI chip architecture and tapeouts * End to end ownership of at least one AI ASIC project * History of product delivery (regardless of ultimate commercial success of said product) * Experience with HBM-based AI chip architecture * Experience in proposing "weird" chip architectures (in any domain, not just AI!)