> Markdown version of [/jobs/ext/4706194-principal-electrical-engineer-asic-fpga-active-secret-onsite](https://www.wearedevelopers.com/jobs/ext/4706194-principal-electrical-engineer-asic-fpga-active-secret-onsite). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Principal Electrical Engineer ASIC/FPGA- Active Secret (Onsite)

- **Company:** RTX
- **Location:** Cedar Rapids, IA, United States
- **Experience:** Expert
- **Salary:** $107,500 - $204,500
- **Contract:** Permanent contract
- **Skills:** Unix, C++ (Programming Language), Digital Architecture, Digital Electronics, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Static Timing Analysis, Subversion, SystemVerilog, Systems Integration, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, ModelSim, Git, Software Version Control
- **Published:** November 13, 2026
- **Apply:** https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-IA-CEDAR-RAPIDS-108--400-Collins-Rd-NE--BLDG-108/Principal-Electrical-Engineer---ASIC-FPGA_01888970

## About the Role

Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance, * RTL coding and simulation in VHDL or Verilog

 * Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
 * Testbench development for the verification of RTL blocks using VHDL or System Verilog.
 * Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
 * Familiarity with revision control concepts and tools (e.g. Git, Subversion)
 * Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience
 * Active and transferable U.S. government issued security clearance is required prior to start date
 * U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance

Qualifications We Prefer

 * Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
 * Ability to work with minimal supervision, team with engineers of a variety of skills and backgrounds, and matrix into projects with aggressive schedules and frequent milestones.
 * Strong oral and written communication skills with the ability to document and present one's work and status
 * ASIC / FPGA lab validation with advanced lab equipment
 * Design for Test (DFT) and manufacturability issues
 * Experience with Unix, scripting, C/C++, and/or Perl

## Description

* Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
 * Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
 * Contribute to engineering estimates for new program pursuits.
 * Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status