> Markdown version of [/jobs/ext/4706993-principal-digital-design-engineer-in-duluth](https://www.wearedevelopers.com/jobs/ext/4706993-principal-digital-design-engineer-in-duluth). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Digital Design Engineer in Duluth - **Company:** Energy Jobline - **Location:** Duluth, GA, United States - **Contract:** Permanent contract - **Skills:** Adobe InDesign, Computer Engineering, Digital Arts, Logic Synthesis of Circuits, Formal Verification, Static Timing Analysis, Subsystems, Verilog, Application Specific Integrated Circuits, Backend, Information Technology, Physical Design - **Published:** November 13, 2026 - **Apply:** https://www.energyjobline.com/job/principal-digital-design-engineer-duluth-32235549 ## About the Role * Education: Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with minimum 12+ years of experience * 12+ years of direct experience in ASIC/IC design with deep knowledge of the entire IC design flow * Experience in architecting digital designs and writing device-level or sub-system specifications. * Fluent in Verilog RTL coding and ASIC design methodology * Expertise in digital design implementation, including logical synthesis and DFT insertion with high coverage * Experience with static timing analysis and creation of place and route constraints * Proficiency in formal verification, linting, and CDC/RDC checking * Knowledge of asynchronous clock crossings and synthesis implications of RTL * Experience implementing and verifying ECOs on RTL, synthesized, and post-route netlists * Competence in developing design constraints for synthesis, STA, and P&R hand-off * Experience with gate-level simulations and understanding the causes and implications of timing violations * Familiarity with ATPG and ATE support (a plus) * Experience in DFT or physical design (a plus) ## Description * Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit * Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set * Apply clocking controls, FSM design, low power techniques, and high-speed design concepts * Participate in design, architecture, and verification reviews * Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking * Create documentation targeting design, verification, and test teams * Assist with the proposal, definition, documentation, and implementation of new features * Mentor and train junior engineers and New College Grad engineers