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# FPGA Developer

- **Company:** ASCENT SERVICES GROUP LLC
- **Location:** Beaverton, OR, United States (Remote available)
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Board Bringup, Code Coverage, Code Review, Encodings, Computer Engineering, Packet Switching, Software Debugging, Network Interface Controllers, Firmware, Formal Verification, Field-Programmable Gate Array (FPGA), Hardware Description Language, Internet Protocol, Signal Processing, Static Timing Analysis, SystemVerilog, VHSIC Hardware Description Language (VHDL), Vivado, Fpga Hardware, Git Flow, Information Technology, Front End Software Development, Physical Design
- **Published:** November 13, 2026
- **Apply:** https://www.careerbuilder.com/job-details/fpga-developer-beaverton-or--4e9d13b3-148f-4469-a194-9ff5d94a8020

## About the Role

FPGA, Economics, Startup, Satellite Communications, Digital Signal Processing (DSP), FPGA, Communications Architecture, IP (Internet Protocol), Packet Switching, Team Player, * B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience.

 * 8+ years of professional FPGA development in SystemVerilog and/or VHDL.
 * Demonstrated experience integrating third-party or vendor IP cores into larger FPGA designs - reading datasheets and user guides, configuring parameters, adapting interfaces, and verifying integrated behavior.
 * Working understanding of packet-based routing and switching concepts (arbitration, buffering, backpressure, link-layer framing) sufficient to integrate and debug routing IP, even if not designing the switch fabric itself.
 * Strong DSP fundamentals and hands-on experience implementing signal processing in fixed-point HDL: filter design, sample-rate conversion, numerically controlled oscillators, and digital down/up-conversion.
 * Practical experience with high-speed serial transceivers (e.g., GTH/GTY, equivalent Intel transceivers) including 8b/10b or 64b/66b encoding, comma alignment, and lane bonding.
 * Proficiency with the full Vivado toolchain: synthesis, implementation, timing analysis (STA), and constraint authoring (XDC/SDC).
 * Strong verification skills, including self-checking testbenches, constrained-random stimulus, and coverage-driven methodology. Comfort with Git-based workflows and code review., * RF and analog front-end experience - working knowledge of RF chains, frequency planning, mixing, image rejection, and the interaction between analog impairments and digital correction.
 * Experience with high-speed converter interfaces such as JESD204B/C, including link bring-up and deterministic latency.
 * Experience with space, defense, or other high-reliability environments, including radiation-tolerant design practices, TMR, scrubbing, and SEU mitigation.
 * Familiarity with AXI/AXI-Stream interconnect and DMA architectures.
 * Background in clock-domain crossing methodology and formal verification of CDC. Experience supporting hardware bring-up with lab instrumentation (logic analyzers, spectrum analyzers, signal generators).

## Description

We are seeking an experienced FPGA Developer to play a critical role in developing and advancing the communications technology behind our next-generation spacecraft. This is an opportunity to take ownership of FPGA development, working across digital signal processing, software-defined radio (SDR), and spacecraft integration.

Youll work with existing modulation, demodulation, and packet-switching IP cores, bringing these systems together while developing custom DSP functionality and the interfaces that allow the spacecraft to command, control, and communicate with the radio. Beyond hands-on RTL development, youll have the opportunity to influence technical direction, solve complex engineering challenges, and help shape the future of our communications architecture.

This is a highly collaborative, hands-on role for an engineer who enjoys technical ownership, solving challenging problems, and seeing their work move from design all the way to orbit.

Responsibilities

Architect, write, and verify synthesizable RTL (SystemVerilog or VHDL) targeting modern FPGAs.

Integrate and configure existing modulation and demodulation, and packet-switching/routing IP cores - parameterizing ports, configuring routing tables, wiring up flow control and error/status interfaces, and validating end-to-end behavior in the surrounding design. Implement DSP blocks in fabric: FIR/CIC/polyphase filters, NCOs and mixers, decimation/interpolation chains, channelizers, and demodulation/synchronization logic.

Develop simulation testbenches (UVM, cocotb, or similar), drive functional and code coverage, and own bring-up on hardware. Take designs through synthesis, place-and-route, and timing closure; analyze utilization, congestion, and Fmax issues and resolve them at the RTL level. Integrate with ADC/DAC front-ends and other mixed-signal interfaces, including clocking, calibration, and lane alignment. Collaborate with systems, firmware, and hardware engineers on interface definitions and HW/SW partitioning. Produce design documentation, interface control documents, and verification reports.