> Markdown version of [/jobs/ext/4721063-technical-director-signal-integrity-engineering](https://www.wearedevelopers.com/jobs/ext/4721063-technical-director-signal-integrity-engineering). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Technical Director, Signal Integrity Engineering - **Company:** Hewlett-Packard Enterprise - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $186,000 - **Contract:** Permanent contract - **Skills:** Computer-Aided Design, Cloud Computing, OrCAD, Signal Integrity, Systems Integration, Hfss, Pcb Layout - **Published:** November 14, 2026 - **Apply:** https://www.careerbuilder.com/job-details/technical-director-signal-integrity-engineering-sunnyvale-ca--dac3fbe1-e6f0-46a4-bdc6-0cfbc29c53c5 ## About the Role Signal Integrity, Signal Integrity, Hewlett-Packard Product Family, Analysis Skills, Cloud Computing, SERDES, Product Development, Technical Leadership, System Integration (SI), Printed Circuit Board (PCB) Layout, * Typically, 15+ years of experience * Must have 5+ years managing signal integrity engineers * Must have knowledge of PAM4 SerDes and Signal Integrity, Clocking, Phase lock Loops * Must have knowledge of SI CAD tools, HFSS, SiWave, Keysight ADS, * Must have knowledge of SI lab equipment, DCAX sampling scope, UXR real time scope, VNA, TDR, Signal Source Analyzer for phase noise measurements * B.S. Electrical Engineering minimum, M.S. Electrical Engineering preferred Knowledge and Skills: * Good people skills, able to motivate people, good communicator, energetic, self starter, positive * Team player able to work across geography with SI Director in India and Senior Director in USA * Knowledge of SI CAD tools, Ansys HFSS, Cadence Allegro, Keysight ADS, Allegro Constraint Manager ## Description The Technical Director, Signal Integrity Engineering is a technical leader responsible for managing a team of SI engineers that implements PAM4 SerDes and develops signal integrity rules for hardware networking systems. In this role, you will work with teams from HW/SW/PCB layout/Manufacturing Test and will have significant impact on HPE by developing new products. Must be technically proficient with PAM4 SerDes and Signal Integrity Design., * Lead team of Signal Integrity engineers working on multiple new programs to implement PAM4 serdes and develop signal integrity rules for HW network systems * Work constructively with other functions HW, SW, PCB layout and other functions to develop new products * Respond and resolve Field Escalations and emergency customer escalations * Work with SI management across geography US/India * Deliver on time with high quality SI deliverables for new products