> Markdown version of [/jobs/ext/4721543-asic-integration-engineer](https://www.wearedevelopers.com/jobs/ext/4721543-asic-integration-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Integration Engineer - **Company:** Experis - **Location:** Carlsbad, CA, United States - **Experience:** Expert - **Salary:** $145,600 - $156,000 - **Contract:** Permanent contract - **Skills:** AI Infrastructure, Cisco - **Published:** November 14, 2026 - **Apply:** https://www.experis.com/en/job/418170/senior-asic-integration-engineer ## About the Role + Bachelor's or Master's Degree in Electrical or Computer Engineering required, with at least 8-10 years of experience. + Experience with lint, CDC, and CLP checker tools, plus working with PnR and synthesis teams. + Hands-on debug experience across complex end-to-end tests spanning analog, digital, and firmware. + Proven ability handling complex block development or mixed-signal ASIC top-level development from concept through post-silicon debug and productization. + Strong communication and presentation skills with the ability to coordinate effectively across engineering disciplines. ## Description Location:Carlsbad, CA or Allentown, PA & Remote is Possible. Key requirement: Candidate should be available to work California times, 9-5 PST. Pay Range: $70 - $75/hr What's the Job? + Own RTL integration of a block/subsystem or complex mixed-signal ASIC top level, ensuring correct connectivity, interfaces, and integration readiness. + Integrate ASIC top-level components such as IO pads, memories, analog macros, and eFuse with multiple embedded CPUs, or demonstrate equivalent experience integrating complex high-speed subsystems across analog, digital, and embedded CPU domains. + Collaborate across cross-functional teams including library, process, PnR, Test Engineering, and Operations to align integration outcomes with downstream needs. + Develop reusable designs and automated flows/scripts that improve team efficiency and reduce integration and debug effort. + Support post-silicon debug and end-to-end validation by working through complex issues across analog, digital, and firmware/test environments. What's Needed?